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qcom,nord
qcom,nord board-id ! ,default_process-nord-1.0-cdsp-i0 6 @ soc M clock-controller@100000 D qcom,gcc-nord qcom,cc-nord-cdsp0 qcom,cc-nord qcom,clock-controller p U 0 @ P ` p / B / B g YGCC_GPLL0_CM_PLL_LUCID_OLE GCC_GPLL1_CM_PLL_LUCID_OLE GCC_GPLL2_CM_PLL_LUCID_OLE GCC_GPLL3_CM_PLL_LUCID_OLE GCC_GPLL4_CM_PLL_LUCID_OLE GCC_GPLL5_CM_PLL_LUCID_OLE GCC_GPLL6_CM_PLL_LUCID_OLE GCC_GPLL7_CM_PLL_LUCID_OLE GCC_JBIST_CM_PLL_JBIST4_OLE GCC_AHB2PHY_SWMAN GCC_AHB2PHY_BROADCAST_SWMAN GCC_CLK_CTL_REG GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY GCC_RPU_XPU4 c M clock-controller@8900000 G qcom,ne_gcc-nord qcom,cc-nord-cdsp0 qcom,cc-nord qcom,clock-controller x U 0 @ P ` p B B YNE_GCC_GPLL0_CM_PLL_LUCID_OLE NE_GCC_GPLL1_CM_PLL_LUCID_OLE NE_GCC_GPLL2_CM_PLL_LUCID_OLE NE_GCC_GPLL3_CM_PLL_LUCID_OLE NE_GCC_GPLL4_CM_PLL_LUCID_OLE NE_GCC_GPLL5_CM_PLL_ZONDA_OLE NE_GCC_GPLL6_CM_PLL_ZONDA_OLE NE_GCC_GPLL7_CM_PLL_ZONDA_OLE NE_GCC_GPLL8_CM_PLL_ZONDA_OLE NE_GCC_JBIST_CM_PLL_JBIST4_OLE NE_GCC_AHB2PHY_SWMAN NE_GCC_AHB2PHY_BROADCAST_SWMAN NE_GCC_NE_CLK_CTL_REG NE_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY NE_GCC_RPU_XPU4 c M clock-controller@1f0c0000 L qcom,nsp_ss_cc_0-nord qcom,cc-nord-cdsp0 qcom,cc-nord qcom,clock-controller H U 0 @ ` p 6 YNSPSS_0_NSP_SS_CC_CORE0_NSP_SS_CC_CORE0_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE1_NSP_SS_CC_CORE1_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE2_NSP_SS_CC_CORE2_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE3_NSP_SS_CC_CORE3_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE4_NSP_SS_CC_CORE4_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_NSP_SS_CC_AHB2PHY_SWMAN NSPSS_0_NSP_SS_CC_NSP_SS_CC_AHB2PHY_BROADCAST_SWMAN NSPSS_0_NSP_SS_CC_NSP_SS_CC_NSP_SS_CC_REG QFPROM_CORR c M clock-controller@8b00000 G qcom,nw_gcc-nord qcom,cc-nord-cdsp0 qcom,cc-nord qcom,clock-controller X U 0 @ P B B 9 YNW_GCC_GPLL0_CM_PLL_LUCID_OLE NW_GCC_GPLL1_CM_PLL_LUCID_OLE NW_GCC_GPLL2_CM_PLL_LUCID_OLE NW_GCC_GPLL3_CM_PLL_LUCID_OLE NW_GCC_GPLL4_CM_PLL_LUCID_OLE NW_GCC_GPLL5_CM_PLL_LUCID_OLE NW_GCC_AHB2PHY_SWMAN NW_GCC_AHB2PHY_BROADCAST_SWMAN NW_GCC_NW_CLK_CTL_REG NW_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY NW_GCC_RPU_XPU4 c M clock-controller@8a00000 G qcom,se_gcc-nord qcom,cc-nord-cdsp0 qcom,cc-nord qcom,clock-controller h U 0 @ P ` p B B v YSE_GCC_GPLL0_CM_PLL_LUCID_OLE SE_GCC_GPLL1_CM_PLL_LUCID_OLE SE_GCC_GPLL2_CM_PLL_LUCID_OLE SE_GCC_GPLL3_CM_PLL_LUCID_OLE SE_GCC_GPLL4_CM_PLL_LUCID_OLE SE_GCC_GPLL5_CM_PLL_LUCID_OLE SE_GCC_GPLL6_CM_PLL_LUCID_OLE SE_GCC_JBIST_CM_PLL_JBIST4_OLE SE_GCC_AHB2PHY_SWMAN SE_GCC_AHB2PHY_BROADCAST_SWMAN SE_GCC_SE_CLK_CTL_REG SE_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY SE_GCC_RPU_XPU4 c M clock-controller@1f340000 O qcom,turing_q6_cc_0-nord qcom,cc-nord-cdsp0 qcom,cc-nord qcom,clock-controller U 4 4@ @ 5 YNSPSS_0_QDSP6SS_PLL_PLL_CM_PLL_LUCID_OLE NSPSS_0_QDSP6SS_Q6V81QA_1_CC_REG NSPSS_0_QDSP6SS_QDSP6_QDSP6_Q6V81QA_1_ACD_MND_NORD_AU c M clock-controller@1f348000 S qcom,turing_q6_hmx_cc_0-nord qcom,cc-nord-cdsp0 qcom,cc-nord qcom,clock-controller U 4 4 @ 5 YNSPSS_0_QDSP6SS_MXU_PLL_MXU_PLL_CM_PLL_LUCID_OLE NSPSS_0_QDSP6SS_MXU_CC_MXU_CC_Q6V81QA_1_HMX_CC_REG NSPSS_0_QDSP6SS_QDSP6_MXU_QDSP6_MXU_Q6V81QA_1_ACD_MND_NORD_AU c M
vdd_mxa qcom,rpmh-arc-regulator p/vcs/vdd_mxa /vcs/vdd_mx mx.lvl M vdd_mxc qcom,rpmh-arc-regulator
p/vcs/vdd_mxc mxc.lvl M vdd_cx qcom,rpmh-arc-regulator p/vcs/vdd_cx cx.lvl M vdd_nsp qcom,rpmh-arc-regulator
p/vcs/vdd_nsp nsp0.lvl M
vdd_nsp_mxc qcom,rpmh-arc-regulator p/vcs/vdd_nsp_mxc /vcs/vdd_nmxc
nmxc.lvl M smem
qcom,smem +
?CORE_TOP_CSR P Z 0 m
@
@ glink qcom,glink @ { proc-info & xport-smem-config edge-01 @ N edge-02 @ ! N edge-03 @ " N xport-qmp-config edge-01 aop_cdsp 0 ipc_router qcom,ipc_router proc-info 0cdsp0
devcfg-glink-xals edge-01 :SMEM Dapss NIPCRTR V ^ g r smp2p qcom,smp2p proc-info z smp2p-interrupts intr-01 intr-02 subsys_instance qcom,subsys_instance ^primary pinctrl@f100000 qcom,nord-pinctrl qcom,pinctrl U
@ 2 3 } summary directconn0 directconn1
'GPIOINTCDSP0 M ipcc
qcom,ipcc ipcc@9003000 qcom,ipcc-protocol U 8 ?MPROC M Z d c 0 1 ! " # $ - . 4 5 2 3 M ipcc@90c1000 qcom,ipcc-protocol U 8 ?COMPUTE_L0 M $ Z t c 0 1 ! " #
/ + $ - . 2 3 6 M ipcc@9181000 qcom,ipcc-protocol U 8 ?COMPUTE_L1 M % Z t c 0 1 ! " #
/ + $ - . 2 3 6 M ipcc@9241000 qcom,ipcc-protocol U 8 ?PERIPH M & Z < c 0 1
! " # $ - M ipcc@9301000 qcom,ipcc-protocol U 8 ?FENCE M ' Z c 0 1 ! " #
/ + $ - . 6 M ipcc_legacy@1f388004 U 8 M ipcc_legacy_cvp qcom,ipcc-legacy 8 8
r timetick timer@1f3a2000 qcom,timetick U : {SystemTimer $ M timer@1f3a3000 qcom,timetick U :0 {WakeUpTimer $ M cxstmtrace@16000000 qcom,stmtrace U x qdss $ 0 0 < L < L 0 tpdm@117c0000
qcom,tpdm U| tpdm_144 tpdm@117c1000
qcom,tpdm U| tpdm_20 tpdm@117c5000
qcom,tpdm U|P tpdm_22 tpdm@117c6000
qcom,tpdm U|` tpdm_87 tpda@117c8000
qcom,tpda U|
null_tpda c $ M sw M qdsp_pm config qcom,config_data * 8 Q l2ConfigRegRange ] f lpassRegRange ] f cores-array core0 o e v core1 o u v core2 o v core3 o v 9 core4 o v : core5 o v ; memories-array memory0 v clocks-array clock0 /clk/cpu v clock1 nsp_ss_cc_aon_clk v clock2 ' nsp_ss_cc_q6ss_ahbs_aon_clk v clock3 / nsp_ss_cc_nspnoc_clk v clock4 1 nsp_ss_cc_noc_hcp_core_clk v clock5 F nsp_ss_cc_nspaux_xo_clk v clock6 E nsp_ss_cc_hcp_core_xo_clk v clock7 9 ! nsp_ss_cc_hcp_core_fint_prog_clk v clock8 : nsp_ss_cc_hcp_core_hcp0_clk v clock9 ; nsp_ss_cc_hcp_core_hcp1_clk v clock10 = nsp_ss_cc_hcp_core_mvr_prog_clk v clock11 > nsp_ss_cc_noc_ubwcd_clk v clock12 t nsp_ss_cc_hcp_core_fint_clk v clock13 u nsp_ss_cc_hcp_core_hcp_clk v clock14 Q nsp_ss_cc_q6ss_ahbs_mxu_aon_clk v clock15 w ! turing_q6_hmx_cc_mxu_cc_core_clk v clock16 y nsp_ss_cc_ubwcd_clk v clock17 z nsp_ss_cc_hcp_core_mvr_clk v clock18 I nsp_ss_cc_hcp_core_hcp_mdc_clk v clock19 K nsp_ss_cc_noc_ubwcd_msf_clk v clock20 L nsp_ss_cc_noc_hcp_core_msf_clk v clock21 # nsp_ss_cc_ubwcd_ahbs_clk v clock22 8 nsp_ss_cc_hcp_core_ahbs_clk v clock23 U nsp_ss_cc_nspcc_div_clk v clock24 V nsp_ss_cc_ceng_proc_clk v clock25 2 nsp_ss_cc_q6ss_q6_axim_clk v busport-array busPort0 ? + 8 busPort1 ? @ + 8 busPort2 ? # + Z 8 busPort3 ? + 8 busPort4 ? % C 8 busPort5 ? 9 L 1 : I 9 u C 8 busPort6 ? ? ' C 8 busPort7 ? : > K C e 8 busPort8 ? ; ; = I L 1 u C e 8 extroute-array extBusRoute0 O Z % extBusRoute1 O Z % extBusRoute2 O Z % mipsroute-array mipsBwRoute0 O Z % pwrDomain-array pwrDomain0 v d r pwrDomain1 v d/core/cpu/latency r pwrDomain2 v dVCS r pwrDomain3 v dnsp_ss_cc_hcp_core_gdsc r pwrDomain4 v dHMX r features-array feature0 P feature1 feature2 feature3 feature4 feature5 feature6 feature7 feature8 feature9 feature10 5 feature11 / feature12 feature13 feature14 $=X feature15 ' feature16 feature17 feature18 feature19 feature20 feature21 feature22 feature23 feature24 feature25 feature26 feature27 feature28 feature29 feature30 feature31 feature32 feature33 feature34 feature35 feature36 feature37 core debugtools eic qcom,eic Z version_tbl qcom,image_version_tbl_idx err_qdi
qcom,err_qdi P
#
pd_mon pd_mon_restart qcom,pd_mon_restart 0 F rcinit qcom,rcinit_cfg rcinit_config_spinor Z w d u0 3 O k rcinit_config Z w !4 3 O k sys_m qcom,sys_m Y servreg
qcom,servreg msm/cdsp/root_pd msm cdsp root_pd L tms_dog
qcom,tms_dog @ @ )@ 8@ D@ M@ [@ f ~ tms_diag qcom,tms_diag / ` debugtrace qcom,debugtrace 8
diag qcom,cdsp_core_diagcfg diagcfg_cmd H [0 v
$ $ $ $ $
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$ $! '$# @$$ T$% n$& $' $( $) diagcfg_param ) = Q i
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> < Y y K 4 F f < X p @ < -Z I diagcfg_early_log g ~ _ diagcfg_f3_trace __symbols__ /soc
/soc/clock-controller@100000 /soc/clock-controller@8900000 /soc/clock-controller@1f0c0000 !/soc/clock-controller@8b00000 (/soc/clock-controller@8a00000 //soc/clock-controller@1f340000 >/soc/clock-controller@1f348000
Q/soc/vdd_mxa
Y/soc/vdd_mxc a/soc/vdd_cx
h/soc/vdd_nsp p/soc/vdd_nsp_mxc |/soc/pinctrl@f100000 /soc/ipcc/ipcc@9003000 /soc/ipcc/ipcc@90c1000 /soc/ipcc/ipcc@9181000 /soc/ipcc/ipcc@9241000 /soc/ipcc/ipcc@9301000 /soc/ipcc_legacy@1f388004 /soc/timetick/timer@1f3a2000 /soc/timetick/timer@1f3a3000 /soc/tpda@117c8000 /sw __fixups__ 7 /soc/pinctrl@f100000:interrupt-parent:0 /soc/ipcc/ipcc@9003000:interrupt-parent:0 /soc/ipcc/ipcc@90c1000:interrupt-parent:0 /soc/ipcc/ipcc@9181000:interrupt-parent:0 /soc/ipcc/ipcc@9241000:interrupt-parent:0 /soc/ipcc/ipcc@9301000:interrupt-parent:0 /soc/ipcc_legacy@1f388004/ipcc_legacy_cvp:interrupt-parent:0 __local_fixups__ soc vdd_nsp_mxc
tpdm@117c0000 tpdm@117c1000 tpdm@117c5000 tpdm@117c6000 model compatible #address-cells #size-cells proc-name chip-info instance-ids phandle reg reg-names #clock-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-init-microvolt qcom,resource-name qcom,all-pd-regulator qcom,lpr-enable qcom,drv-id parent0-supply smem-this-host smem-version-offset core-top-csr-str tcsr-base mutex-offsets-data wonce-offsets supported-hosts remote-host fifo-size mtu-size irq-out qos-max-rate channel-name mailbox-area-size-bytes master-mailbox-size-bytes max-tx-pending-items is-master mailbox-desc-start host-name transport remote-ss ch-name options priority stack-size intents host-id fflags max-entries dest proc irq value ngpios width egpio gpio-controller #gpio-cells interrupt-parent interrupts interrupt-types interrupt-names summary-targetproc global-ctxt-name client protocol-name protocol-idx #signals client-mapping out-mask timer-name timer-freq timer-num timer-interrupt base_port num_ports dbg_regs pwrdbg_ctrl_reg tpdm_name tpda tpda_port dataset cmb_size tpda_name atid port_occupied_mask tpath THREAD_NUMBER OVERHANG_VOTE_TIMEOUT_MS DEBUG_LEVEL baseAddr physAddr coreId pwrDomain coreClockInstances masterBusPortInstances slaveBusPortInstances numInstances memId clkId clkType clkCntlType clkName clkSrcId memoryId portConnection busClk regProgClocks icbarbMaster accessPort icbarbSlave masterPort slavePort pwrDomainName pwrDomainType intrReinitTrigger intrReinitDone securityClocks state min max eic_crash_enable eic_crash_type eic_crash_delay image_idx pd_timeout_exit_msec threshold_timeout_sec num_pdrs_log pd_mon_restart_enable pd_mon_dump_disable rcinit_term_err_fatal_enable rcinit_term_timeout rcinit_term_timeout_group_0 rcinit_term_timeout_group_1 rcinit_term_timeout_group_2 rcinit_term_timeout_group_3 rcinit_term_timeout_group_4 rcinit_term_timeout_group_5 rcinit_term_timeout_group_6 rcinit_term_timeout_group_7 rcinit_term_latency_enable ssctl_srv sys_m_smem_ssr_res servreg_local_domain servreg_soc_name servreg_domain_name servreg_subdomain_name servreg_qmi_instance_id wdog_nmi_time wdog_bite_time wdog_bark_time wdog_status wdog_ctl wdog_bite_nmi wdog_reset wdog_nmi_time_data_bmsk wdog_bite_time_data_bmsk wdog_bark_time_data_bmsk wdog_ctl_wdog_to_nmi_en_bmsk wdog_ctl_wdog_to_nmi_en_shft wdog_ctl_enable_bmsk wdog_ctl_enable_shft wdog_reset_wdog_reset_shft image_id qdss_service_id diag_cmd_request_f diag_dcm_cmd_reg_test_base diag_ulogdiag_processor_id diag_subsys_id_base diag_stress_test_loopback diag_start_stress_test_f diag_get_cmd_reg_tbl diag_legacy_health_count_base diag_get_max_req_pkt_len diag_delay_health_count_base diag_flow_control_count_base diag_subsys_mask_retrieval_base diag_f3_trace_set_config diag_tx_mode_config diag_get_time_api diag_stress_test_delayed_rsp diag_uimage_health_stats diag_start_stress_test_adv_f diag_health_stats_base diag_get_set_drain_param diag_set_drain_prop diag_health_report_config diag_get_set_client_settings diag_lock_buffer_api diag_query_enable diag_get_drop_per diag_instance_id_base diag_err_ulog_size diag_debug_ulog_size diag_cmd_ulog_size diag_data_ulog_size diag_qdss_ulog_size diag_ctrl_ulog_size diag_listener_ulog_size diag_sendbuf_dbg_ulog_size diag_mpd_drain_timer_len diag_mpd_buf_commit_thresh_per diag_mpd_buf_drain_thresh_per diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_drain_timer_len diag_event_send_max diag_event_heap_size diag_ctrl_send_buf_size diag_ctrl_read_buf_size diag_cmd_read_buf_size diag_event_sec_heap_size diag_dci_read_buf_size diag_rsp_heap_size diag_heap_size diag_f3_trace_buf_size diag_buf_size diag_rsp_alloc_retry_timer_len diag_mask_notify_timer_len diag_tx_sleep_threshold_default diag_tx_sleep_time_default diag_core_pd_drain_threshold diag_sio_timeout_timer_len diag_cmd_read_tout_timer_len diag_max_active_listeners diag_many_drain_per_mark diag_few_drain_per_mark diag_hdlc_pad_len diag_stress_task_sleep_complete diag_buf_commit_threshold diag_buffer_default_lock_state diag_deferrable_timer diag_deferrable_timer_ex diag_send_data_buf_size_max diag_min_send_data_size diag_msg_fmt_str_arg_size diag_event_rpt_pkt_len_size_nrt diag_event_rpt_pkt_size_nrt diag_event_send_max_nrt diag_event_timer_len_nrt diag_tx_sleep_threshold_nrt diag_tx_sleep_time_nrt diag_drain_timer_len_nrt diagbuf_commit_threshold_nrt diag_mpd_commit_thresh_nrt_per diag_uimage_drain_timer_len diag_uimage_buf_high_per_wm diag_uimage_f3_trace_buf_size diag_early_log_control diag_early_log_mask diag_early_event_mask diag_early_message_mask diag_f3_trace_control diag_f3_trace_detail_mask diag_f3_trace_version soc gcc ne_gcc nsp_ss_cc_0 nw_gcc se_gcc turing_q6_cc_0 turing_q6_hmx_cc_0 vdd_mxa vdd_mxc vdd_cx vdd_nsp vdd_nsp_mxc tlmm ipcc_mproc ipcc_compute_l0 ipcc_compute_l1 ipcc_periph ipcc_fence ipcc_legacy SystemTimer WakeUpTimer null_tpda sw intc
t 8 a ( a
qcom,nord
qcom,nord board-id ! ,default_process-nord-1.0-cdsp-i1 6 @ soc M smem
qcom,smem U d
xCORE_TOP_CSR 0
@
@ glink qcom,glink @ proc-info _ xport-smem-config edge-01 @ N edge-02 @ ! N edge-03 @ " N xport-qmp-config edge-01
aop_cdsp1 7 L V ipc_router qcom,ipc_router proc-info icdsp1 s
devcfg-glink-xals edge-01 vSMEM apss IPCRTR smp2p qcom,smp2p proc-info smp2p-interrupts intr-01 intr-02 subsys_instance qcom,subsys_instance
secondary clock-controller@100000 D qcom,gcc-nord qcom,cc-nord-cdsp1 qcom,cc-nord qcom,clock-controller p 0 @ P ` p / B / B g GCC_GPLL0_CM_PLL_LUCID_OLE GCC_GPLL1_CM_PLL_LUCID_OLE GCC_GPLL2_CM_PLL_LUCID_OLE GCC_GPLL3_CM_PLL_LUCID_OLE GCC_GPLL4_CM_PLL_LUCID_OLE GCC_GPLL5_CM_PLL_LUCID_OLE GCC_GPLL6_CM_PLL_LUCID_OLE GCC_GPLL7_CM_PLL_LUCID_OLE GCC_JBIST_CM_PLL_JBIST4_OLE GCC_AHB2PHY_SWMAN GCC_AHB2PHY_BROADCAST_SWMAN GCC_CLK_CTL_REG GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY GCC_RPU_XPU4 M clock-controller@8900000 G qcom,ne_gcc-nord qcom,cc-nord-cdsp1 qcom,cc-nord qcom,clock-controller x 0 @ P ` p B B NE_GCC_GPLL0_CM_PLL_LUCID_OLE NE_GCC_GPLL1_CM_PLL_LUCID_OLE NE_GCC_GPLL2_CM_PLL_LUCID_OLE NE_GCC_GPLL3_CM_PLL_LUCID_OLE NE_GCC_GPLL4_CM_PLL_LUCID_OLE NE_GCC_GPLL5_CM_PLL_ZONDA_OLE NE_GCC_GPLL6_CM_PLL_ZONDA_OLE NE_GCC_GPLL7_CM_PLL_ZONDA_OLE NE_GCC_GPLL8_CM_PLL_ZONDA_OLE NE_GCC_JBIST_CM_PLL_JBIST4_OLE NE_GCC_AHB2PHY_SWMAN NE_GCC_AHB2PHY_BROADCAST_SWMAN NE_GCC_NE_CLK_CTL_REG NE_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY NE_GCC_RPU_XPU4 M clock-controller@1f4c0000 L qcom,nsp_ss_cc_0-nord qcom,cc-nord-cdsp1 qcom,cc-nord qcom,clock-controller H L L L L0 L@ L` Lp L 6 NSPSS_0_NSP_SS_CC_CORE0_NSP_SS_CC_CORE0_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE1_NSP_SS_CC_CORE1_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE2_NSP_SS_CC_CORE2_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE3_NSP_SS_CC_CORE3_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE4_NSP_SS_CC_CORE4_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_NSP_SS_CC_AHB2PHY_SWMAN NSPSS_0_NSP_SS_CC_NSP_SS_CC_AHB2PHY_BROADCAST_SWMAN NSPSS_0_NSP_SS_CC_NSP_SS_CC_NSP_SS_CC_REG QFPROM_CORR M clock-controller@8b00000 G qcom,nw_gcc-nord qcom,cc-nord-cdsp1 qcom,cc-nord qcom,clock-controller X 0 @ P B B 9 NW_GCC_GPLL0_CM_PLL_LUCID_OLE NW_GCC_GPLL1_CM_PLL_LUCID_OLE NW_GCC_GPLL2_CM_PLL_LUCID_OLE NW_GCC_GPLL3_CM_PLL_LUCID_OLE NW_GCC_GPLL4_CM_PLL_LUCID_OLE NW_GCC_GPLL5_CM_PLL_LUCID_OLE NW_GCC_AHB2PHY_SWMAN NW_GCC_AHB2PHY_BROADCAST_SWMAN NW_GCC_NW_CLK_CTL_REG NW_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY NW_GCC_RPU_XPU4 M clock-controller@8a00000 G qcom,se_gcc-nord qcom,cc-nord-cdsp1 qcom,cc-nord qcom,clock-controller h 0 @ P ` p B B v SE_GCC_GPLL0_CM_PLL_LUCID_OLE SE_GCC_GPLL1_CM_PLL_LUCID_OLE SE_GCC_GPLL2_CM_PLL_LUCID_OLE SE_GCC_GPLL3_CM_PLL_LUCID_OLE SE_GCC_GPLL4_CM_PLL_LUCID_OLE SE_GCC_GPLL5_CM_PLL_LUCID_OLE SE_GCC_GPLL6_CM_PLL_LUCID_OLE SE_GCC_JBIST_CM_PLL_JBIST4_OLE SE_GCC_AHB2PHY_SWMAN SE_GCC_AHB2PHY_BROADCAST_SWMAN SE_GCC_SE_CLK_CTL_REG SE_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY SE_GCC_RPU_XPU4 M clock-controller@1f740000 O qcom,turing_q6_cc_0-nord qcom,cc-nord-cdsp1 qcom,cc-nord qcom,clock-controller t t@ @ u NSPSS_0_QDSP6SS_PLL_PLL_CM_PLL_LUCID_OLE NSPSS_0_QDSP6SS_Q6V81QA_1_CC_REG NSPSS_0_QDSP6SS_QDSP6_QDSP6_Q6V81QA_1_ACD_MND_NORD_AU M clock-controller@1f748000 S qcom,turing_q6_hmx_cc_0-nord qcom,cc-nord-cdsp1 qcom,cc-nord qcom,clock-controller t t @ u NSPSS_0_QDSP6SS_MXU_PLL_MXU_PLL_CM_PLL_LUCID_OLE NSPSS_0_QDSP6SS_MXU_CC_MXU_CC_Q6V81QA_1_HMX_CC_REG NSPSS_0_QDSP6SS_QDSP6_MXU_QDSP6_MXU_Q6V81QA_1_ACD_MND_NORD_AU M
ipcc
qcom,ipcc ipcc@9004000 qcom,ipcc-protocol MPROC " 3 > d G 0 1 ! " # $ - . 4 5 2 3 M ipcc@90c2000 qcom,ipcc-protocol COMPUTE_L0 " 3 $ > t G 0 1 ! " #
/ + $ - . 2 3 6 M ipcc@9182000 qcom,ipcc-protocol COMPUTE_L1 " 3 % > t G 0 1 ! " #
/ + $ - . 2 3 6 M
ipcc@9242000 qcom,ipcc-protocol PERIPH " 3 & > < G 0 1
! " # $ - M ipcc@9302000 qcom,ipcc-protocol FENCE " 3 ' > G 0 1 ! " #
/ + $ - . 6 M ipcc_legacy@1f788004 x M ipcc_legacy_cvp qcom,ipcc-legacy q
" 3 V timetick timer@1f7a2000 qcom,timetick z _SystemTimer j$ u M timer@1f7a3000 qcom,timetick z0 _WakeUpTimer j$ u M vdd_mxa qcom,rpmh-arc-regulator /vcs/vdd_mxa /vcs/vdd_mx mx.lvl M vdd_mxc qcom,rpmh-arc-regulator
/vcs/vdd_mxc mxc.lvl M vdd_cx qcom,rpmh-arc-regulator /vcs/vdd_cx cx.lvl M vdd_nsp qcom,rpmh-arc-regulator /vcs/vdd_nsp /vcs/vdd_nsp1 nsp1.lvl M vdd_nsp_mxc qcom,rpmh-arc-regulator /vcs/vdd_nsp_mxc /vcs/vdd_nmxc , nmxc.lvl M pinctrl@f100000 qcom,nord-pinctrl qcom,pinctrl ; B s H N ^ " 3 @ 2 3 j } zsummary directconn0 directconn1
GPIOINTCDSP1 M cxstmtrace@16000000 qcom,stmtrace } qdss $ p p | L | F L F p tpdm@117e0000
qcom,tpdm ~ tpdm_82 tpdm@117e1000
qcom,tpdm ~ tpdm_136 tpdm@117e5000
qcom,tpdm ~P tpdm_156 tpdm@117e6000
qcom,tpdm ~` tpdm_25 tpda@117e8000
qcom,tpda ~
null_tpda c ' M sw M qdsp_pm config qcom,config_data - ; T l2ConfigRegRange ` i lpassRegRange ` i cores-array core0 r e y core1 r u y core2 r y core3 r y 9 core4 r y : core5 r y ; memories-array memory0 y clocks-array clock0 /clk/cpu y clock1 nsp_ss_cc_aon_clk y clock2 ' nsp_ss_cc_q6ss_ahbs_aon_clk y clock3 / nsp_ss_cc_nspnoc_clk y clock4 1 nsp_ss_cc_noc_hcp_core_clk y clock5 F nsp_ss_cc_nspaux_xo_clk y clock6 E nsp_ss_cc_hcp_core_xo_clk y clock7 9 ! nsp_ss_cc_hcp_core_fint_prog_clk y clock8 : nsp_ss_cc_hcp_core_hcp0_clk y clock9 ; nsp_ss_cc_hcp_core_hcp1_clk y clock10 = nsp_ss_cc_hcp_core_mvr_prog_clk y clock11 > nsp_ss_cc_noc_ubwcd_clk y clock12 t nsp_ss_cc_hcp_core_fint_clk y clock13 u nsp_ss_cc_hcp_core_hcp_clk y clock14 Q nsp_ss_cc_q6ss_ahbs_mxu_aon_clk y clock15 w ! turing_q6_hmx_cc_mxu_cc_core_clk y clock16 y nsp_ss_cc_ubwcd_clk y clock17 z nsp_ss_cc_hcp_core_mvr_clk y clock18 I nsp_ss_cc_hcp_core_hcp_mdc_clk y clock19 K nsp_ss_cc_noc_ubwcd_msf_clk y clock20 L nsp_ss_cc_noc_hcp_core_msf_clk y clock21 # nsp_ss_cc_ubwcd_ahbs_clk y clock22 8 nsp_ss_cc_hcp_core_ahbs_clk y clock23 U nsp_ss_cc_nspcc_div_clk y clock24 V nsp_ss_cc_ceng_proc_clk y clock25 2 nsp_ss_cc_q6ss_q6_axim_clk y busport-array busPort0 {
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; = I L 1 u F e ; extroute-array extBusRoute0 R ] % extBusRoute1 R ] % extBusRoute2 R ] % mipsroute-array mipsBwRoute0 R ] % pwrDomain-array pwrDomain0 y g u pwrDomain1 y g/core/cpu/latency u pwrDomain2 y gVCS u pwrDomain3 y gnsp_ss_cc_hcp_core_gdsc u pwrDomain4 y gHMX u features-array feature0 P feature1 feature2 feature3 feature4 feature5 feature6 feature7 feature8 feature9 feature10 5 feature11 / feature12 feature13 feature14 $=X feature15 ' feature16 feature17 feature18 feature19 feature20 feature21 feature22 feature23 feature24 feature25 feature26 feature27 feature28 feature29 feature30 feature31 feature32 feature33 feature34 feature35 feature36 feature37 core debugtools eic qcom,eic Z version_tbl qcom,image_version_tbl_idx err_qdi
qcom,err_qdi P &
pd_mon pd_mon_restart qcom,pd_mon_restart 3 I rcinit qcom,rcinit_cfg rcinit_config_spinor ] z d u0 6 R n rcinit_config ] z !4 6 R n sys_m qcom,sys_m y servreg
qcom,servreg msm/cdsp1/root_pd msm cdsp1 root_pd } tms_dog
qcom,tms_dog @ @ ,@ ;@ G@ P@ ^@ i tms_diag qcom,tms_diag 2 debugtrace qcom,debugtrace ; diag qcom,cdsp_core_diagcfg diagcfg_cmd K ^ y ( ( ( ( (
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/soc/clock-controller@100000 /soc/clock-controller@8900000 /soc/clock-controller@1f4c0000 $/soc/clock-controller@8b00000 +/soc/clock-controller@8a00000 2/soc/clock-controller@1f740000 A/soc/clock-controller@1f748000 T/soc/ipcc/ipcc@9004000 _/soc/ipcc/ipcc@90c2000 o/soc/ipcc/ipcc@9182000 /soc/ipcc/ipcc@9242000 /soc/ipcc/ipcc@9302000 /soc/ipcc_legacy@1f788004 /soc/timetick/timer@1f7a2000 /soc/timetick/timer@1f7a3000
/soc/vdd_mxa
/soc/vdd_mxc /soc/vdd_cx
/soc/vdd_nsp /soc/vdd_nsp_mxc /soc/pinctrl@f100000 /soc/tpda@117e8000 /sw __fixups__ 7 /soc/ipcc/ipcc@9004000:interrupt-parent:0 /soc/ipcc/ipcc@90c2000:interrupt-parent:0 /soc/ipcc/ipcc@9182000:interrupt-parent:0 /soc/ipcc/ipcc@9242000:interrupt-parent:0 /soc/ipcc/ipcc@9302000:interrupt-parent:0 /soc/ipcc_legacy@1f788004/ipcc_legacy_cvp:interrupt-parent:0 /soc/pinctrl@f100000:interrupt-parent:0 __local_fixups__ soc vdd_nsp_mxc , tpdm@117e0000 tpdm@117e1000 tpdm@117e5000 tpdm@117e6000 model compatible #address-cells #size-cells proc-name chip-info instance-ids phandle smem-this-host smem-version-offset core-top-csr-str tcsr-base mutex-offsets-data wonce-offsets supported-hosts remote-host fifo-size mtu-size irq-out qos-max-rate channel-name mailbox-area-size-bytes master-mailbox-size-bytes max-tx-pending-items is-master mailbox-desc-start host-name id transport remote-ss ch-name options priority stack-size intents host-id fflags max-entries dest proc irq value reg reg-names #clock-cells client protocol-name protocol-idx interrupt-parent interrupts #signals client-mapping out-mask timer-name timer-freq timer-num timer-interrupt regulator-name regulator-min-microvolt regulator-max-microvolt regulator-init-microvolt qcom,resource-name qcom,all-pd-regulator qcom,lpr-enable qcom,drv-id parent0-supply ngpios width egpio gpio-controller #gpio-cells interrupt-types interrupt-names summary-targetproc global-ctxt-name base_port num_ports dbg_regs pwrdbg_ctrl_reg tpdm_name tpda tpda_port dataset cmb_size tpda_name atid port_occupied_mask tpath THREAD_NUMBER OVERHANG_VOTE_TIMEOUT_MS DEBUG_LEVEL baseAddr physAddr coreId pwrDomain coreClockInstances masterBusPortInstances slaveBusPortInstances numInstances memId clkId clkType clkCntlType clkName clkSrcId memoryId portConnection busClk regProgClocks icbarbMaster accessPort icbarbSlave masterPort slavePort pwrDomainName pwrDomainType intrReinitTrigger intrReinitDone securityClocks state min max eic_crash_enable eic_crash_type eic_crash_delay image_idx pd_timeout_exit_msec threshold_timeout_sec num_pdrs_log pd_mon_restart_enable pd_mon_dump_disable rcinit_term_err_fatal_enable rcinit_term_timeout rcinit_term_timeout_group_0 rcinit_term_timeout_group_1 rcinit_term_timeout_group_2 rcinit_term_timeout_group_3 rcinit_term_timeout_group_4 rcinit_term_timeout_group_5 rcinit_term_timeout_group_6 rcinit_term_timeout_group_7 rcinit_term_latency_enable ssctl_srv sys_m_smem_ssr_res servreg_local_domain servreg_soc_name servreg_domain_name servreg_subdomain_name servreg_qmi_instance_id wdog_nmi_time wdog_bite_time wdog_bark_time wdog_status wdog_ctl wdog_bite_nmi wdog_reset wdog_nmi_time_data_bmsk wdog_bite_time_data_bmsk wdog_bark_time_data_bmsk wdog_ctl_wdog_to_nmi_en_bmsk wdog_ctl_wdog_to_nmi_en_shft wdog_ctl_enable_bmsk wdog_ctl_enable_shft wdog_reset_wdog_reset_shft image_id qdss_service_id diag_cmd_request_f diag_dcm_cmd_reg_test_base diag_ulogdiag_processor_id diag_subsys_id_base diag_stress_test_loopback diag_start_stress_test_f diag_get_cmd_reg_tbl diag_legacy_health_count_base diag_get_max_req_pkt_len diag_delay_health_count_base diag_flow_control_count_base diag_subsys_mask_retrieval_base diag_f3_trace_set_config diag_tx_mode_config diag_get_time_api diag_stress_test_delayed_rsp diag_uimage_health_stats diag_start_stress_test_adv_f diag_health_stats_base diag_get_set_drain_param diag_set_drain_prop diag_health_report_config diag_get_set_client_settings diag_lock_buffer_api diag_query_enable diag_get_drop_per diag_instance_id_base diag_err_ulog_size diag_debug_ulog_size diag_cmd_ulog_size diag_data_ulog_size diag_qdss_ulog_size diag_ctrl_ulog_size diag_listener_ulog_size diag_sendbuf_dbg_ulog_size diag_mpd_drain_timer_len diag_mpd_buf_commit_thresh_per diag_mpd_buf_drain_thresh_per diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_drain_timer_len diag_event_send_max diag_event_heap_size diag_ctrl_send_buf_size diag_ctrl_read_buf_size diag_cmd_read_buf_size diag_event_sec_heap_size diag_dci_read_buf_size diag_rsp_heap_size diag_heap_size diag_f3_trace_buf_size diag_buf_size diag_rsp_alloc_retry_timer_len diag_mask_notify_timer_len diag_tx_sleep_threshold_default diag_tx_sleep_time_default diag_core_pd_drain_threshold diag_sio_timeout_timer_len diag_cmd_read_tout_timer_len diag_max_active_listeners diag_many_drain_per_mark diag_few_drain_per_mark diag_hdlc_pad_len diag_stress_task_sleep_complete diag_buf_commit_threshold diag_buffer_default_lock_state diag_deferrable_timer diag_deferrable_timer_ex diag_send_data_buf_size_max diag_min_send_data_size diag_msg_fmt_str_arg_size diag_event_rpt_pkt_len_size_nrt diag_event_rpt_pkt_size_nrt diag_event_send_max_nrt diag_event_timer_len_nrt diag_tx_sleep_threshold_nrt diag_tx_sleep_time_nrt diag_drain_timer_len_nrt diagbuf_commit_threshold_nrt diag_mpd_commit_thresh_nrt_per diag_uimage_drain_timer_len diag_uimage_buf_high_per_wm diag_uimage_f3_trace_buf_size diag_early_log_control diag_early_log_mask diag_early_event_mask diag_early_message_mask diag_f3_trace_control diag_f3_trace_detail_mask diag_f3_trace_version soc gcc ne_gcc nsp_ss_cc_0 nw_gcc se_gcc turing_q6_cc_0 turing_q6_hmx_cc_0 ipcc_mproc ipcc_compute_l0 ipcc_compute_l1 ipcc_periph ipcc_fence ipcc_legacy SystemTimer WakeUpTimer vdd_mxa vdd_mxc vdd_cx vdd_nsp vdd_nsp_mxc tlmm null_tpda sw intc
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qcom,nord
qcom,nord board-id ! ,default_process-nord-1.0-cdsp-i2 6 @ soc M smem
qcom,smem U d
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@ glink qcom,glink @ proc-info _ xport-smem-config edge-01 @ N edge-02 @ ! N edge-03 @ " N xport-qmp-config edge-01
aop_cdsp2 7 L V 0 ipc_router qcom,ipc_router proc-info icdsp2 s
devcfg-glink-xals edge-01 vSMEM apss IPCRTR smp2p qcom,smp2p proc-info smp2p-interrupts intr-01 intr-02 subsys_instance qcom,subsys_instance
secondary clock-controller@100000 D qcom,gcc-nord qcom,cc-nord-cdsp2 qcom,cc-nord qcom,clock-controller p 0 @ P ` p / B / B g GCC_GPLL0_CM_PLL_LUCID_OLE GCC_GPLL1_CM_PLL_LUCID_OLE GCC_GPLL2_CM_PLL_LUCID_OLE GCC_GPLL3_CM_PLL_LUCID_OLE GCC_GPLL4_CM_PLL_LUCID_OLE GCC_GPLL5_CM_PLL_LUCID_OLE GCC_GPLL6_CM_PLL_LUCID_OLE GCC_GPLL7_CM_PLL_LUCID_OLE GCC_JBIST_CM_PLL_JBIST4_OLE GCC_AHB2PHY_SWMAN GCC_AHB2PHY_BROADCAST_SWMAN GCC_CLK_CTL_REG GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY GCC_RPU_XPU4 M clock-controller@8900000 G qcom,ne_gcc-nord qcom,cc-nord-cdsp2 qcom,cc-nord qcom,clock-controller x 0 @ P ` p B B NE_GCC_GPLL0_CM_PLL_LUCID_OLE NE_GCC_GPLL1_CM_PLL_LUCID_OLE NE_GCC_GPLL2_CM_PLL_LUCID_OLE NE_GCC_GPLL3_CM_PLL_LUCID_OLE NE_GCC_GPLL4_CM_PLL_LUCID_OLE NE_GCC_GPLL5_CM_PLL_ZONDA_OLE NE_GCC_GPLL6_CM_PLL_ZONDA_OLE NE_GCC_GPLL7_CM_PLL_ZONDA_OLE NE_GCC_GPLL8_CM_PLL_ZONDA_OLE NE_GCC_JBIST_CM_PLL_JBIST4_OLE NE_GCC_AHB2PHY_SWMAN NE_GCC_AHB2PHY_BROADCAST_SWMAN NE_GCC_NE_CLK_CTL_REG NE_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY NE_GCC_RPU_XPU4 M clock-controller@1f8c0000 L qcom,nsp_ss_cc_0-nord qcom,cc-nord-cdsp2 qcom,cc-nord qcom,clock-controller H 0 @ ` p 6 NSPSS_0_NSP_SS_CC_CORE0_NSP_SS_CC_CORE0_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE1_NSP_SS_CC_CORE1_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE2_NSP_SS_CC_CORE2_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE3_NSP_SS_CC_CORE3_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE4_NSP_SS_CC_CORE4_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_NSP_SS_CC_AHB2PHY_SWMAN NSPSS_0_NSP_SS_CC_NSP_SS_CC_AHB2PHY_BROADCAST_SWMAN NSPSS_0_NSP_SS_CC_NSP_SS_CC_NSP_SS_CC_REG QFPROM_CORR M clock-controller@8b00000 G qcom,nw_gcc-nord qcom,cc-nord-cdsp2 qcom,cc-nord qcom,clock-controller X 0 @ P B B 9 NW_GCC_GPLL0_CM_PLL_LUCID_OLE NW_GCC_GPLL1_CM_PLL_LUCID_OLE NW_GCC_GPLL2_CM_PLL_LUCID_OLE NW_GCC_GPLL3_CM_PLL_LUCID_OLE NW_GCC_GPLL4_CM_PLL_LUCID_OLE NW_GCC_GPLL5_CM_PLL_LUCID_OLE NW_GCC_AHB2PHY_SWMAN NW_GCC_AHB2PHY_BROADCAST_SWMAN NW_GCC_NW_CLK_CTL_REG NW_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY NW_GCC_RPU_XPU4 M clock-controller@8a00000 G qcom,se_gcc-nord qcom,cc-nord-cdsp2 qcom,cc-nord qcom,clock-controller h 0 @ P ` p B B v SE_GCC_GPLL0_CM_PLL_LUCID_OLE SE_GCC_GPLL1_CM_PLL_LUCID_OLE SE_GCC_GPLL2_CM_PLL_LUCID_OLE SE_GCC_GPLL3_CM_PLL_LUCID_OLE SE_GCC_GPLL4_CM_PLL_LUCID_OLE SE_GCC_GPLL5_CM_PLL_LUCID_OLE SE_GCC_GPLL6_CM_PLL_LUCID_OLE SE_GCC_JBIST_CM_PLL_JBIST4_OLE SE_GCC_AHB2PHY_SWMAN SE_GCC_AHB2PHY_BROADCAST_SWMAN SE_GCC_SE_CLK_CTL_REG SE_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY SE_GCC_RPU_XPU4 M clock-controller@1fb40000 O qcom,turing_q6_cc_0-nord qcom,cc-nord-cdsp2 qcom,cc-nord qcom,clock-controller @ @ NSPSS_0_QDSP6SS_PLL_PLL_CM_PLL_LUCID_OLE NSPSS_0_QDSP6SS_Q6V81QA_1_CC_REG NSPSS_0_QDSP6SS_QDSP6_QDSP6_Q6V81QA_1_ACD_MND_NORD_AU M clock-controller@1fb48000 S qcom,turing_q6_hmx_cc_0-nord qcom,cc-nord-cdsp2 qcom,cc-nord qcom,clock-controller @ NSPSS_0_QDSP6SS_MXU_PLL_MXU_PLL_CM_PLL_LUCID_OLE NSPSS_0_QDSP6SS_MXU_CC_MXU_CC_Q6V81QA_1_HMX_CC_REG NSPSS_0_QDSP6SS_QDSP6_MXU_QDSP6_MXU_Q6V81QA_1_ACD_MND_NORD_AU M
ipcc
qcom,ipcc ipcc@9005000 qcom,ipcc-protocol 0 MPROC " 3 > d G 0 1 ! " # $ - . 4 5 2 3 M ipcc@90c3000 qcom,ipcc-protocol 0 COMPUTE_L0 " 3 $ > t G 0 1 ! " #
/ + $ - . 2 3 6 M ipcc@9183000 qcom,ipcc-protocol 0 COMPUTE_L1 " 3 % > t G 0 1 ! " #
/ + $ - . 2 3 6 M
ipcc@9243000 qcom,ipcc-protocol 0 PERIPH " 3 & > < G 0 1
! " # $ - M ipcc@9303000 qcom,ipcc-protocol 0 FENCE " 3 ' > G 0 1 ! " #
/ + $ - . 6 M ipcc_legacy@1fb88004 M ipcc_legacy_cvp qcom,ipcc-legacy q
" 3 V timetick timer@1fba2000 qcom,timetick _SystemTimer j$ u M timer@1fba3000 qcom,timetick 0 _WakeUpTimer j$ u M vdd_mxa qcom,rpmh-arc-regulator /vcs/vdd_mxa /vcs/vdd_mx mx.lvl M vdd_mxc qcom,rpmh-arc-regulator
/vcs/vdd_mxc mxc.lvl M vdd_cx qcom,rpmh-arc-regulator /vcs/vdd_cx cx.lvl M vdd_nsp qcom,rpmh-arc-regulator /vcs/vdd_nsp /vcs/vdd_nsp2 nsp2.lvl M vdd_nsp_mxc qcom,rpmh-arc-regulator /vcs/vdd_nsp_mxc /vcs/vdd_nmxc , nmxc.lvl M pinctrl@f100000 qcom,nord-pinctrl qcom,pinctrl ; B s H N ^ " 3 @ 2 3 j } zsummary directconn0 directconn1
GPIOINTCDSP2 M cxstmtrace@16000000 qcom,stmtrace qdss $ L L tpdm@118c0000
qcom,tpdm tpdm_90 tpdm@118c1000
qcom,tpdm tpdm_26 tpdm@118c5000
qcom,tpdm P tpdm_28 tpdm@118c6000
qcom,tpdm ` tpdm_138 tpda@118c8000
qcom,tpda
null_tpda c ' M sw M qdsp_pm config qcom,config_data - ; T l2ConfigRegRange ` i lpassRegRange ` i cores-array core0 r e y core1 r u y core2 r y core3 r y 9 core4 r y : core5 r y ; memories-array memory0 y clocks-array clock0 /clk/cpu y clock1 nsp_ss_cc_aon_clk y clock2 ' nsp_ss_cc_q6ss_ahbs_aon_clk y clock3 / nsp_ss_cc_nspnoc_clk y clock4 1 nsp_ss_cc_noc_hcp_core_clk y clock5 F nsp_ss_cc_nspaux_xo_clk y clock6 E nsp_ss_cc_hcp_core_xo_clk y clock7 9 ! nsp_ss_cc_hcp_core_fint_prog_clk y clock8 : nsp_ss_cc_hcp_core_hcp0_clk y clock9 ; nsp_ss_cc_hcp_core_hcp1_clk y clock10 = nsp_ss_cc_hcp_core_mvr_prog_clk y clock11 > nsp_ss_cc_noc_ubwcd_clk y clock12 t nsp_ss_cc_hcp_core_fint_clk y clock13 u nsp_ss_cc_hcp_core_hcp_clk y clock14 Q nsp_ss_cc_q6ss_ahbs_mxu_aon_clk y clock15 w ! turing_q6_hmx_cc_mxu_cc_core_clk y clock16 y nsp_ss_cc_ubwcd_clk y clock17 z nsp_ss_cc_hcp_core_mvr_clk y clock18 I nsp_ss_cc_hcp_core_hcp_mdc_clk y clock19 K nsp_ss_cc_noc_ubwcd_msf_clk y clock20 L nsp_ss_cc_noc_hcp_core_msf_clk y clock21 # nsp_ss_cc_ubwcd_ahbs_clk y clock22 8 nsp_ss_cc_hcp_core_ahbs_clk y clock23 U nsp_ss_cc_nspcc_div_clk y clock24 V nsp_ss_cc_ceng_proc_clk y clock25 2 nsp_ss_cc_q6ss_q6_axim_clk y busport-array busPort0 {
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; = I L 1 u F e ; extroute-array extBusRoute0 R ] % extBusRoute1 R ] % extBusRoute2 R ] % mipsroute-array mipsBwRoute0 R ] % pwrDomain-array pwrDomain0 y g u pwrDomain1 y g/core/cpu/latency u pwrDomain2 y gVCS u pwrDomain3 y gnsp_ss_cc_hcp_core_gdsc u pwrDomain4 y gHMX u features-array feature0 P feature1 feature2 feature3 feature4 feature5 feature6 feature7 feature8 feature9 feature10 5 feature11 / feature12 feature13 feature14 $=X feature15 ' feature16 feature17 feature18 feature19 feature20 feature21 feature22 feature23 feature24 feature25 feature26 feature27 feature28 feature29 feature30 feature31 feature32 feature33 feature34 feature35 feature36 feature37 core debugtools eic qcom,eic Z version_tbl qcom,image_version_tbl_idx err_qdi
qcom,err_qdi P &
pd_mon pd_mon_restart qcom,pd_mon_restart 3 I rcinit qcom,rcinit_cfg rcinit_config_spinor ] z d u0 6 R n rcinit_config ] z !4 6 R n sys_m qcom,sys_m servreg
qcom,servreg msm/cdsp2/root_pd msm cdsp2 root_pd ~ tms_dog
qcom,tms_dog @ @ ,@ ;@ G@ P@ ^@ i tms_diag qcom,tms_diag 2 X debugtrace qcom,debugtrace ; diag qcom,cdsp_core_diagcfg diagcfg_cmd K ^p y# 2 2 2 2 2
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/soc/vdd_mxa
/soc/vdd_mxc /soc/vdd_cx
/soc/vdd_nsp /soc/vdd_nsp_mxc /soc/pinctrl@f100000 /soc/tpda@118c8000 /sw __fixups__ 7 /soc/ipcc/ipcc@9005000:interrupt-parent:0 /soc/ipcc/ipcc@90c3000:interrupt-parent:0 /soc/ipcc/ipcc@9183000:interrupt-parent:0 /soc/ipcc/ipcc@9243000:interrupt-parent:0 /soc/ipcc/ipcc@9303000:interrupt-parent:0 /soc/ipcc_legacy@1fb88004/ipcc_legacy_cvp:interrupt-parent:0 /soc/pinctrl@f100000:interrupt-parent:0 __local_fixups__ soc vdd_nsp_mxc , tpdm@118c0000 tpdm@118c1000 tpdm@118c5000 tpdm@118c6000 model compatible #address-cells #size-cells proc-name chip-info instance-ids phandle smem-this-host smem-version-offset core-top-csr-str tcsr-base mutex-offsets-data wonce-offsets supported-hosts remote-host fifo-size mtu-size irq-out qos-max-rate channel-name mailbox-area-size-bytes master-mailbox-size-bytes max-tx-pending-items is-master mailbox-desc-start host-name id transport remote-ss ch-name options priority stack-size intents host-id fflags max-entries dest proc irq value reg reg-names #clock-cells client protocol-name protocol-idx interrupt-parent interrupts #signals client-mapping out-mask timer-name timer-freq timer-num timer-interrupt regulator-name regulator-min-microvolt regulator-max-microvolt regulator-init-microvolt qcom,resource-name qcom,all-pd-regulator qcom,lpr-enable qcom,drv-id parent0-supply ngpios width egpio gpio-controller #gpio-cells interrupt-types interrupt-names summary-targetproc global-ctxt-name base_port num_ports dbg_regs pwrdbg_ctrl_reg tpdm_name tpda tpda_port dataset cmb_size tpda_name atid port_occupied_mask tpath THREAD_NUMBER OVERHANG_VOTE_TIMEOUT_MS DEBUG_LEVEL baseAddr physAddr coreId pwrDomain coreClockInstances masterBusPortInstances slaveBusPortInstances numInstances memId clkId clkType clkCntlType clkName clkSrcId memoryId portConnection busClk regProgClocks icbarbMaster accessPort icbarbSlave masterPort slavePort pwrDomainName pwrDomainType intrReinitTrigger intrReinitDone securityClocks state min max eic_crash_enable eic_crash_type eic_crash_delay image_idx pd_timeout_exit_msec threshold_timeout_sec num_pdrs_log pd_mon_restart_enable pd_mon_dump_disable rcinit_term_err_fatal_enable rcinit_term_timeout rcinit_term_timeout_group_0 rcinit_term_timeout_group_1 rcinit_term_timeout_group_2 rcinit_term_timeout_group_3 rcinit_term_timeout_group_4 rcinit_term_timeout_group_5 rcinit_term_timeout_group_6 rcinit_term_timeout_group_7 rcinit_term_latency_enable ssctl_srv sys_m_smem_ssr_res servreg_local_domain servreg_soc_name servreg_domain_name servreg_subdomain_name servreg_qmi_instance_id wdog_nmi_time wdog_bite_time wdog_bark_time wdog_status wdog_ctl wdog_bite_nmi wdog_reset wdog_nmi_time_data_bmsk wdog_bite_time_data_bmsk wdog_bark_time_data_bmsk wdog_ctl_wdog_to_nmi_en_bmsk wdog_ctl_wdog_to_nmi_en_shft wdog_ctl_enable_bmsk wdog_ctl_enable_shft wdog_reset_wdog_reset_shft image_id qdss_service_id diag_cmd_request_f diag_dcm_cmd_reg_test_base diag_ulogdiag_processor_id diag_subsys_id_base diag_stress_test_loopback diag_start_stress_test_f diag_get_cmd_reg_tbl diag_legacy_health_count_base diag_get_max_req_pkt_len diag_delay_health_count_base diag_flow_control_count_base diag_subsys_mask_retrieval_base diag_f3_trace_set_config diag_tx_mode_config diag_get_time_api diag_stress_test_delayed_rsp diag_uimage_health_stats diag_start_stress_test_adv_f diag_health_stats_base diag_get_set_drain_param diag_set_drain_prop diag_health_report_config diag_get_set_client_settings diag_lock_buffer_api diag_query_enable diag_get_drop_per diag_instance_id_base diag_err_ulog_size diag_debug_ulog_size diag_cmd_ulog_size diag_data_ulog_size diag_qdss_ulog_size diag_ctrl_ulog_size diag_listener_ulog_size diag_sendbuf_dbg_ulog_size diag_mpd_drain_timer_len diag_mpd_buf_commit_thresh_per diag_mpd_buf_drain_thresh_per diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_drain_timer_len diag_event_send_max diag_event_heap_size diag_ctrl_send_buf_size diag_ctrl_read_buf_size diag_cmd_read_buf_size diag_event_sec_heap_size diag_dci_read_buf_size diag_rsp_heap_size diag_heap_size diag_f3_trace_buf_size diag_buf_size diag_rsp_alloc_retry_timer_len diag_mask_notify_timer_len diag_tx_sleep_threshold_default diag_tx_sleep_time_default diag_core_pd_drain_threshold diag_sio_timeout_timer_len diag_cmd_read_tout_timer_len diag_max_active_listeners diag_many_drain_per_mark diag_few_drain_per_mark diag_hdlc_pad_len diag_stress_task_sleep_complete diag_buf_commit_threshold diag_buffer_default_lock_state diag_deferrable_timer diag_deferrable_timer_ex diag_send_data_buf_size_max diag_min_send_data_size diag_msg_fmt_str_arg_size diag_event_rpt_pkt_len_size_nrt diag_event_rpt_pkt_size_nrt diag_event_send_max_nrt diag_event_timer_len_nrt diag_tx_sleep_threshold_nrt diag_tx_sleep_time_nrt diag_drain_timer_len_nrt diagbuf_commit_threshold_nrt diag_mpd_commit_thresh_nrt_per diag_uimage_drain_timer_len diag_uimage_buf_high_per_wm diag_uimage_f3_trace_buf_size diag_early_log_control diag_early_log_mask diag_early_event_mask diag_early_message_mask diag_f3_trace_control diag_f3_trace_detail_mask diag_f3_trace_version soc gcc ne_gcc nsp_ss_cc_0 nw_gcc se_gcc turing_q6_cc_0 turing_q6_hmx_cc_0 ipcc_mproc ipcc_compute_l0 ipcc_compute_l1 ipcc_periph ipcc_fence ipcc_legacy SystemTimer WakeUpTimer vdd_mxa vdd_mxc vdd_cx vdd_nsp vdd_nsp_mxc tlmm null_tpda sw intc
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aop_cdsp3 7 L V @ ipc_router qcom,ipc_router proc-info icdsp3 s
devcfg-glink-xals edge-01 vSMEM apss IPCRTR smp2p qcom,smp2p proc-info smp2p-interrupts intr-01 intr-02 subsys_instance qcom,subsys_instance
secondary clock-controller@100000 D qcom,gcc-nord qcom,cc-nord-cdsp3 qcom,cc-nord qcom,clock-controller p 0 @ P ` p / B / B g GCC_GPLL0_CM_PLL_LUCID_OLE GCC_GPLL1_CM_PLL_LUCID_OLE GCC_GPLL2_CM_PLL_LUCID_OLE GCC_GPLL3_CM_PLL_LUCID_OLE GCC_GPLL4_CM_PLL_LUCID_OLE GCC_GPLL5_CM_PLL_LUCID_OLE GCC_GPLL6_CM_PLL_LUCID_OLE GCC_GPLL7_CM_PLL_LUCID_OLE GCC_JBIST_CM_PLL_JBIST4_OLE GCC_AHB2PHY_SWMAN GCC_AHB2PHY_BROADCAST_SWMAN GCC_CLK_CTL_REG GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY GCC_RPU_XPU4 M clock-controller@8900000 G qcom,ne_gcc-nord qcom,cc-nord-cdsp3 qcom,cc-nord qcom,clock-controller x 0 @ P ` p B B NE_GCC_GPLL0_CM_PLL_LUCID_OLE NE_GCC_GPLL1_CM_PLL_LUCID_OLE NE_GCC_GPLL2_CM_PLL_LUCID_OLE NE_GCC_GPLL3_CM_PLL_LUCID_OLE NE_GCC_GPLL4_CM_PLL_LUCID_OLE NE_GCC_GPLL5_CM_PLL_ZONDA_OLE NE_GCC_GPLL6_CM_PLL_ZONDA_OLE NE_GCC_GPLL7_CM_PLL_ZONDA_OLE NE_GCC_GPLL8_CM_PLL_ZONDA_OLE NE_GCC_JBIST_CM_PLL_JBIST4_OLE NE_GCC_AHB2PHY_SWMAN NE_GCC_AHB2PHY_BROADCAST_SWMAN NE_GCC_NE_CLK_CTL_REG NE_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY NE_GCC_RPU_XPU4 M clock-controller@1fcc0000 L qcom,nsp_ss_cc_0-nord qcom,cc-nord-cdsp3 qcom,cc-nord qcom,clock-controller H 0 @ ` p ̀ 6 NSPSS_0_NSP_SS_CC_CORE0_NSP_SS_CC_CORE0_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE1_NSP_SS_CC_CORE1_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE2_NSP_SS_CC_CORE2_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE3_NSP_SS_CC_CORE3_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_CORE4_NSP_SS_CC_CORE4_CM_PLL_LUCID_OLE NSPSS_0_NSP_SS_CC_NSP_SS_CC_AHB2PHY_SWMAN NSPSS_0_NSP_SS_CC_NSP_SS_CC_AHB2PHY_BROADCAST_SWMAN NSPSS_0_NSP_SS_CC_NSP_SS_CC_NSP_SS_CC_REG QFPROM_CORR M clock-controller@8b00000 G qcom,nw_gcc-nord qcom,cc-nord-cdsp3 qcom,cc-nord qcom,clock-controller X 0 @ P B B 9 NW_GCC_GPLL0_CM_PLL_LUCID_OLE NW_GCC_GPLL1_CM_PLL_LUCID_OLE NW_GCC_GPLL2_CM_PLL_LUCID_OLE NW_GCC_GPLL3_CM_PLL_LUCID_OLE NW_GCC_GPLL4_CM_PLL_LUCID_OLE NW_GCC_GPLL5_CM_PLL_LUCID_OLE NW_GCC_AHB2PHY_SWMAN NW_GCC_AHB2PHY_BROADCAST_SWMAN NW_GCC_NW_CLK_CTL_REG NW_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY NW_GCC_RPU_XPU4 M clock-controller@8a00000 G qcom,se_gcc-nord qcom,cc-nord-cdsp3 qcom,cc-nord qcom,clock-controller h 0 @ P ` p B B v SE_GCC_GPLL0_CM_PLL_LUCID_OLE SE_GCC_GPLL1_CM_PLL_LUCID_OLE SE_GCC_GPLL2_CM_PLL_LUCID_OLE SE_GCC_GPLL3_CM_PLL_LUCID_OLE SE_GCC_GPLL4_CM_PLL_LUCID_OLE SE_GCC_GPLL5_CM_PLL_LUCID_OLE SE_GCC_GPLL6_CM_PLL_LUCID_OLE SE_GCC_JBIST_CM_PLL_JBIST4_OLE SE_GCC_AHB2PHY_SWMAN SE_GCC_AHB2PHY_BROADCAST_SWMAN SE_GCC_SE_CLK_CTL_REG SE_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY SE_GCC_RPU_XPU4 M clock-controller@1ff40000 O qcom,turing_q6_cc_0-nord qcom,cc-nord-cdsp3 qcom,cc-nord qcom,clock-controller @ @ NSPSS_0_QDSP6SS_PLL_PLL_CM_PLL_LUCID_OLE NSPSS_0_QDSP6SS_Q6V81QA_1_CC_REG NSPSS_0_QDSP6SS_QDSP6_QDSP6_Q6V81QA_1_ACD_MND_NORD_AU M clock-controller@1ff48000 S qcom,turing_q6_hmx_cc_0-nord qcom,cc-nord-cdsp3 qcom,cc-nord qcom,clock-controller @ NSPSS_0_QDSP6SS_MXU_PLL_MXU_PLL_CM_PLL_LUCID_OLE NSPSS_0_QDSP6SS_MXU_CC_MXU_CC_Q6V81QA_1_HMX_CC_REG NSPSS_0_QDSP6SS_QDSP6_MXU_QDSP6_MXU_Q6V81QA_1_ACD_MND_NORD_AU M
ipcc
qcom,ipcc ipcc@9006000 qcom,ipcc-protocol 1 MPROC " 3 > d G 0 1 ! " # $ - . 4 5 2 3 M ipcc@90c4000 qcom,ipcc-protocol 1 COMPUTE_L0 " 3 $ > t G 0 1 ! " #
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ipcc@9244000 qcom,ipcc-protocol 1 PERIPH " 3 & > < G 0 1
! " # $ - M ipcc@9304000 qcom,ipcc-protocol 1 FENCE " 3 ' > G 0 1 ! " #
/ + $ - . 6 M ipcc_legacy@1ff88004 M ipcc_legacy_cvp qcom,ipcc-legacy q
" 3 V timetick timer@1ffa2000 qcom,timetick _SystemTimer j$ u M timer@1ffa3000 qcom,timetick 0 _WakeUpTimer j$ u M vdd_mxa qcom,rpmh-arc-regulator /vcs/vdd_mxa /vcs/vdd_mx mx.lvl M vdd_mxc qcom,rpmh-arc-regulator
/vcs/vdd_mxc mxc.lvl M vdd_cx qcom,rpmh-arc-regulator /vcs/vdd_cx cx.lvl M vdd_nsp qcom,rpmh-arc-regulator /vcs/vdd_nsp /vcs/vdd_nsp3 nsp3.lvl M vdd_nsp_mxc qcom,rpmh-arc-regulator /vcs/vdd_nsp_mxc /vcs/vdd_nmxc , nmxc.lvl M pinctrl@f100000 qcom,nord-pinctrl qcom,pinctrl ; B s H N ^ " 3 @ 2 3 j } zsummary directconn0 directconn1
GPIOINTCDSP3 M cxstmtrace@16000000 qcom,stmtrace qdss $ L L tpdm@118e0000
qcom,tpdm tpdm_29 tpdm@118e1000
qcom,tpdm tpdm_92 tpdm@118e5000
qcom,tpdm P tpdm_93 tpdm@118e6000
qcom,tpdm ` tpdm_32 tpda@118e8000
qcom,tpda
null_tpda c ' M sw M qdsp_pm config qcom,config_data - ; T l2ConfigRegRange ` i lpassRegRange ` i cores-array core0 r e y core1 r u y core2 r y core3 r y 9 core4 r y : core5 r y ; memories-array memory0 y clocks-array clock0 /clk/cpu y clock1 nsp_ss_cc_aon_clk y clock2 ' nsp_ss_cc_q6ss_ahbs_aon_clk y clock3 / nsp_ss_cc_nspnoc_clk y clock4 1 nsp_ss_cc_noc_hcp_core_clk y clock5 F nsp_ss_cc_nspaux_xo_clk y clock6 E nsp_ss_cc_hcp_core_xo_clk y clock7 9 ! nsp_ss_cc_hcp_core_fint_prog_clk y clock8 : nsp_ss_cc_hcp_core_hcp0_clk y clock9 ; nsp_ss_cc_hcp_core_hcp1_clk y clock10 = nsp_ss_cc_hcp_core_mvr_prog_clk y clock11 > nsp_ss_cc_noc_ubwcd_clk y clock12 t nsp_ss_cc_hcp_core_fint_clk y clock13 u nsp_ss_cc_hcp_core_hcp_clk y clock14 Q nsp_ss_cc_q6ss_ahbs_mxu_aon_clk y clock15 w ! turing_q6_hmx_cc_mxu_cc_core_clk y clock16 y nsp_ss_cc_ubwcd_clk y clock17 z nsp_ss_cc_hcp_core_mvr_clk y clock18 I nsp_ss_cc_hcp_core_hcp_mdc_clk y clock19 K nsp_ss_cc_noc_ubwcd_msf_clk y clock20 L nsp_ss_cc_noc_hcp_core_msf_clk y clock21 # nsp_ss_cc_ubwcd_ahbs_clk y clock22 8 nsp_ss_cc_hcp_core_ahbs_clk y clock23 U nsp_ss_cc_nspcc_div_clk y clock24 V nsp_ss_cc_ceng_proc_clk y clock25 2 nsp_ss_cc_q6ss_q6_axim_clk y busport-array busPort0 {
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/soc/clock-controller@100000 /soc/clock-controller@8900000 /soc/clock-controller@1fcc0000 $/soc/clock-controller@8b00000 +/soc/clock-controller@8a00000 2/soc/clock-controller@1ff40000 A/soc/clock-controller@1ff48000 T/soc/ipcc/ipcc@9006000 _/soc/ipcc/ipcc@90c4000 o/soc/ipcc/ipcc@9184000 /soc/ipcc/ipcc@9244000 /soc/ipcc/ipcc@9304000 /soc/ipcc_legacy@1ff88004 /soc/timetick/timer@1ffa2000 /soc/timetick/timer@1ffa3000
/soc/vdd_mxa
/soc/vdd_mxc /soc/vdd_cx
/soc/vdd_nsp /soc/vdd_nsp_mxc /soc/pinctrl@f100000 /soc/tpda@118e8000 /sw __fixups__ 7 /soc/ipcc/ipcc@9006000:interrupt-parent:0 /soc/ipcc/ipcc@90c4000:interrupt-parent:0 /soc/ipcc/ipcc@9184000:interrupt-parent:0 /soc/ipcc/ipcc@9244000:interrupt-parent:0 /soc/ipcc/ipcc@9304000:interrupt-parent:0 /soc/ipcc_legacy@1ff88004/ipcc_legacy_cvp:interrupt-parent:0 /soc/pinctrl@f100000:interrupt-parent:0 __local_fixups__ soc vdd_nsp_mxc , tpdm@118e0000 tpdm@118e1000 tpdm@118e5000 tpdm@118e6000 model compatible #address-cells #size-cells proc-name chip-info instance-ids phandle smem-this-host smem-version-offset core-top-csr-str tcsr-base mutex-offsets-data wonce-offsets supported-hosts remote-host fifo-size mtu-size irq-out qos-max-rate channel-name mailbox-area-size-bytes master-mailbox-size-bytes max-tx-pending-items is-master mailbox-desc-start host-name id transport remote-ss ch-name options priority stack-size intents host-id fflags max-entries dest proc irq value reg reg-names #clock-cells client protocol-name protocol-idx interrupt-parent interrupts #signals client-mapping out-mask timer-name timer-freq timer-num timer-interrupt regulator-name regulator-min-microvolt regulator-max-microvolt regulator-init-microvolt qcom,resource-name qcom,all-pd-regulator qcom,lpr-enable qcom,drv-id parent0-supply ngpios width egpio gpio-controller #gpio-cells interrupt-types interrupt-names summary-targetproc global-ctxt-name base_port num_ports dbg_regs pwrdbg_ctrl_reg tpdm_name tpda tpda_port dataset cmb_size tpda_name atid port_occupied_mask tpath THREAD_NUMBER OVERHANG_VOTE_TIMEOUT_MS DEBUG_LEVEL baseAddr physAddr coreId pwrDomain coreClockInstances masterBusPortInstances slaveBusPortInstances numInstances memId clkId clkType clkCntlType clkName clkSrcId memoryId portConnection busClk regProgClocks icbarbMaster accessPort icbarbSlave masterPort slavePort pwrDomainName pwrDomainType intrReinitTrigger intrReinitDone securityClocks state min max eic_crash_enable eic_crash_type eic_crash_delay image_idx pd_timeout_exit_msec threshold_timeout_sec num_pdrs_log pd_mon_restart_enable pd_mon_dump_disable rcinit_term_err_fatal_enable rcinit_term_timeout rcinit_term_timeout_group_0 rcinit_term_timeout_group_1 rcinit_term_timeout_group_2 rcinit_term_timeout_group_3 rcinit_term_timeout_group_4 rcinit_term_timeout_group_5 rcinit_term_timeout_group_6 rcinit_term_timeout_group_7 rcinit_term_latency_enable ssctl_srv sys_m_smem_ssr_res servreg_local_domain servreg_soc_name servreg_domain_name servreg_subdomain_name servreg_qmi_instance_id wdog_nmi_time wdog_bite_time wdog_bark_time wdog_status wdog_ctl wdog_bite_nmi wdog_reset wdog_nmi_time_data_bmsk wdog_bite_time_data_bmsk wdog_bark_time_data_bmsk wdog_ctl_wdog_to_nmi_en_bmsk wdog_ctl_wdog_to_nmi_en_shft wdog_ctl_enable_bmsk wdog_ctl_enable_shft wdog_reset_wdog_reset_shft image_id qdss_service_id diag_cmd_request_f diag_dcm_cmd_reg_test_base diag_ulogdiag_processor_id diag_subsys_id_base diag_stress_test_loopback diag_start_stress_test_f diag_get_cmd_reg_tbl diag_legacy_health_count_base diag_get_max_req_pkt_len diag_delay_health_count_base diag_flow_control_count_base diag_subsys_mask_retrieval_base diag_f3_trace_set_config diag_tx_mode_config diag_get_time_api diag_stress_test_delayed_rsp diag_uimage_health_stats diag_start_stress_test_adv_f diag_health_stats_base diag_get_set_drain_param diag_set_drain_prop diag_health_report_config diag_get_set_client_settings diag_lock_buffer_api diag_query_enable diag_get_drop_per diag_instance_id_base diag_err_ulog_size diag_debug_ulog_size diag_cmd_ulog_size diag_data_ulog_size diag_qdss_ulog_size diag_ctrl_ulog_size diag_listener_ulog_size diag_sendbuf_dbg_ulog_size diag_mpd_drain_timer_len diag_mpd_buf_commit_thresh_per diag_mpd_buf_drain_thresh_per diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_drain_timer_len diag_event_send_max diag_event_heap_size diag_ctrl_send_buf_size diag_ctrl_read_buf_size diag_cmd_read_buf_size diag_event_sec_heap_size diag_dci_read_buf_size diag_rsp_heap_size diag_heap_size diag_f3_trace_buf_size diag_buf_size diag_rsp_alloc_retry_timer_len diag_mask_notify_timer_len diag_tx_sleep_threshold_default diag_tx_sleep_time_default diag_core_pd_drain_threshold diag_sio_timeout_timer_len diag_cmd_read_tout_timer_len diag_max_active_listeners diag_many_drain_per_mark diag_few_drain_per_mark diag_hdlc_pad_len diag_stress_task_sleep_complete diag_buf_commit_threshold diag_buffer_default_lock_state diag_deferrable_timer diag_deferrable_timer_ex diag_send_data_buf_size_max diag_min_send_data_size diag_msg_fmt_str_arg_size diag_event_rpt_pkt_len_size_nrt diag_event_rpt_pkt_size_nrt diag_event_send_max_nrt diag_event_timer_len_nrt diag_tx_sleep_threshold_nrt diag_tx_sleep_time_nrt diag_drain_timer_len_nrt diagbuf_commit_threshold_nrt diag_mpd_commit_thresh_nrt_per diag_uimage_drain_timer_len diag_uimage_buf_high_per_wm diag_uimage_f3_trace_buf_size diag_early_log_control diag_early_log_mask diag_early_event_mask diag_early_message_mask diag_f3_trace_control diag_f3_trace_detail_mask diag_f3_trace_version soc gcc ne_gcc nsp_ss_cc_0 nw_gcc se_gcc turing_q6_cc_0 turing_q6_hmx_cc_0 ipcc_mproc ipcc_compute_l0 ipcc_compute_l1 ipcc_periph ipcc_fence ipcc_legacy SystemTimer WakeUpTimer vdd_mxa vdd_mxc vdd_cx vdd_nsp vdd_nsp_mxc tlmm null_tpda sw intc h
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