Sid Gifari From Gifari Industries - BD Cyber Security Team
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Editing: adsp_dtb.mbn
ELF ( �4 4 � � � 0 0 p @ h h � �� �p 8 q ( f p� qcom,nord qcom,nord board-id ' ,default_process-nord-1.0-adsp-i0-audio 6 � @ soc M smem qcom,smem U d xCORE_TOP_CSR �� � 0 � @ @ glink qcom,glink ` � proc-info _ xport-smem-config edge-01 � � @ � � � N edge-02 � � @ � � � N edge-03 � � @ � � � N edge-04 � � @ � � ! � N edge-05 � � @ � � " � N xport-qmp-config edge-01 �aop_adsp � 7 � L V @ ipc_router qcom,ipc_router proc-info iadsp0 s devcfg-glink-xals edge-01 vSMEM �apss �IPCRTR � �� � � � � � edge-02 vSMEM �apss_1_0_0 �IPCRTR � �� � � � � � edge-03 vSMEM �apss_2_0_0 �IPCRTR � �� � � � � � smp2p qcom,smp2p proc-info � � � smp2p-interrupts intr-01 � � � intr-02 � � � clock-controller@af00000 7 qcom,disp_cc_0-nord qcom,cc-nord qcom,clock-controller 8 � � � � �0 �` �p � � ? �MDSS_0_DISP_CC_PLL0_DISP_CC_PLL0_CM_PLL_LUCID_OLE MDSS_0_DISP_CC_PLL1_DISP_CC_PLL1_CM_PLL_LUCID_OLE MDSS_0_DISP_CC_PLL2_DISP_CC_PLL2_CM_PLL_ZONDA_OLE MDSS_0_DISP_CC_PLL3_DISP_CC_PLL3_CM_PLL_ZONDA_OLE MDSS_0_DISP_CC_DISP_CC_AHB2PHY_SWMAN MDSS_0_DISP_CC_DISP_CC_AHB2PHY_BROADCAST_SWMAN MDSS_0_DISP_CC_DISP_CC_DISP_CC_REG � M clock-controller@8d00000 7 qcom,disp_cc_1-nord qcom,cc-nord qcom,clock-controller 8 �� � � �0 �` �p Ѐ � ? �MDSS_1_DISP_CC_PLL0_DISP_CC_PLL0_CM_PLL_LUCID_OLE MDSS_1_DISP_CC_PLL1_DISP_CC_PLL1_CM_PLL_LUCID_OLE MDSS_1_DISP_CC_PLL2_DISP_CC_PLL2_CM_PLL_ZONDA_OLE MDSS_1_DISP_CC_PLL3_DISP_CC_PLL3_CM_PLL_ZONDA_OLE MDSS_1_DISP_CC_DISP_CC_AHB2PHY_SWMAN MDSS_1_DISP_CC_DISP_CC_AHB2PHY_BROADCAST_SWMAN MDSS_1_DISP_CC_DISP_CC_DISP_CC_REG � M clock-controller@100000 1 qcom,gcc-nord qcom,cc-nord qcom,clock-controller p � 0 @ P ` p � � � / B / B g �GCC_GPLL0_CM_PLL_LUCID_OLE GCC_GPLL1_CM_PLL_LUCID_OLE GCC_GPLL2_CM_PLL_LUCID_OLE GCC_GPLL3_CM_PLL_LUCID_OLE GCC_GPLL4_CM_PLL_LUCID_OLE GCC_GPLL5_CM_PLL_LUCID_OLE GCC_GPLL6_CM_PLL_LUCID_OLE GCC_GPLL7_CM_PLL_LUCID_OLE GCC_JBIST_CM_PLL_JBIST4_OLE GCC_AHB2PHY_SWMAN GCC_AHB2PHY_BROADCAST_SWMAN GCC_CLK_CTL_REG GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY GCC_RPU_XPU4 � M clock-controller@5000000 < qcom,hpass_audio_cc-nord qcom,cc-nord qcom,clock-controller 8 � ` p � p � �HPASS_AUDIO_CC HPASS_AUDIO_CC_PLL1_CM_PLL_ZONDA_OLE HPASS_AUDIO_CC_PLL2_CM_PLL_ZONDA_OLE HPASS_AUDIO_CC_CM_PLL_JBIST4_OLE HPASS_AUDIO_CC_AHB2PHY_SWMAN HPASS_AUDIO_CC_AHB2PHY_BROADCAST_SWMAN HPASS_AUDIO_CC_HPASS_AUDIO_CC_REG � M clock-controller@5500000 6 qcom,hpass_cc-nord qcom,cc-nord qcom,clock-controller 0 �P � P P` Pp P� X � � �HPASS_CC HPASS_CC_DIG_PLL_CM_PLL_LUCID_OLE HPASS_CC_AHB2PHY_SWMAN HPASS_CC_AHB2PHY_BROADCAST_SWMAN HPASS_CC_HPASS_CC_REG HPASS_HPASS_TCSR_REGS � M clock-controller@4d80000 < qcom,hpass_lpmla_cc-nord qcom,cc-nord qcom,clock-controller ( �� � � �` �p @ � �HPASS_LPMLA_CC HPASS_LPMLA_CC_DIG_PLL_CM_PLL_LUCID_OLE HPASS_LPMLA_CC_AHB2PHY_SWMAN HPASS_LPMLA_CC_AHB2PHY_BROADCAST_SWMAN HPASS_LPMLA_CC_HPASS_LPMLA_CC_REG � M clock-controller@4c40000 ; qcom,hpass_q6_cc_0-nord qcom,cc-nord qcom,clock-controller �� Ā � K �HPASS_0_QDSP6SS_PLL_PLL_CM_PLL_LUCID_OLE HPASS_0_QDSP6SS_Q6V81DGB_1_CC_REG � M clock-controller@8900000 4 qcom,ne_gcc-nord qcom,cc-nord qcom,clock-controller x �� � � �0 �@ �P �` �p �� �� �� �� � � B � B � �NE_GCC_GPLL0_CM_PLL_LUCID_OLE NE_GCC_GPLL1_CM_PLL_LUCID_OLE NE_GCC_GPLL2_CM_PLL_LUCID_OLE NE_GCC_GPLL3_CM_PLL_LUCID_OLE NE_GCC_GPLL4_CM_PLL_LUCID_OLE NE_GCC_GPLL5_CM_PLL_ZONDA_OLE NE_GCC_GPLL6_CM_PLL_ZONDA_OLE NE_GCC_GPLL7_CM_PLL_ZONDA_OLE NE_GCC_GPLL8_CM_PLL_ZONDA_OLE NE_GCC_JBIST_CM_PLL_JBIST4_OLE NE_GCC_AHB2PHY_SWMAN NE_GCC_AHB2PHY_BROADCAST_SWMAN NE_GCC_NE_CLK_CTL_REG NE_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY NE_GCC_RPU_XPU4 � M clock-controller@8b00000 4 qcom,nw_gcc-nord qcom,cc-nord qcom,clock-controller X �� � � �0 �@ �P �� �� � � B � B 9 �NW_GCC_GPLL0_CM_PLL_LUCID_OLE NW_GCC_GPLL1_CM_PLL_LUCID_OLE NW_GCC_GPLL2_CM_PLL_LUCID_OLE NW_GCC_GPLL3_CM_PLL_LUCID_OLE NW_GCC_GPLL4_CM_PLL_LUCID_OLE NW_GCC_GPLL5_CM_PLL_LUCID_OLE NW_GCC_AHB2PHY_SWMAN NW_GCC_AHB2PHY_BROADCAST_SWMAN NW_GCC_NW_CLK_CTL_REG NW_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY NW_GCC_RPU_XPU4 � M clock-controller@8a00000 4 qcom,se_gcc-nord qcom,cc-nord qcom,clock-controller h �� � � �0 �@ �P �` �p �� �� � � B � B v �SE_GCC_GPLL0_CM_PLL_LUCID_OLE SE_GCC_GPLL1_CM_PLL_LUCID_OLE SE_GCC_GPLL2_CM_PLL_LUCID_OLE SE_GCC_GPLL3_CM_PLL_LUCID_OLE SE_GCC_GPLL4_CM_PLL_LUCID_OLE SE_GCC_GPLL5_CM_PLL_LUCID_OLE SE_GCC_GPLL6_CM_PLL_LUCID_OLE SE_GCC_JBIST_CM_PLL_JBIST4_OLE SE_GCC_AHB2PHY_SWMAN SE_GCC_AHB2PHY_BROADCAST_SWMAN SE_GCC_SE_CLK_CTL_REG SE_GCC_RPU_GCC_RPUQ11_200_CL36L12_LE_SA_SY SE_GCC_RPU_XPU4 � M clock-controller@1f40000 5 qcom,tcsr_cc-nord qcom,cc-nord qcom,clock-controller �� � �TCSR_TCSR_REGS TLMM_REG � M cesta@5333000 # qcom,hpass_cesta-nord qcom,cc-nord ( �30 34 38 3X 3^ @ �HPASS_CRMB HPASS_CRMB_PT HPASS_CRMC HPASS_CRMV HPASS_CRM_COMMON M ipcc qcom,ipcc ipcc@9002000 qcom,ipcc-protocol � � MPROC ���� - . 8 d A 0 1 ! " # $ - . 4 5 2 3 M ipcc@90c0000 qcom,ipcc-protocol � � COMPUTE_L0 ���� - + 8 t A 0 1 ! " # / + $ - . 2 3 6 M ipcc@9180000 qcom,ipcc-protocol � � COMPUTE_L1 ���� - , 8 t A 0 1 ! " # / + $ - . 2 3 6 M ipcc@9240000 qcom,ipcc-protocol � � PERIPH ���� - / 8 < A 0 1 ! " # $ - M ipcc@9300000 qcom,ipcc-protocol � � FENCE ���� - - 8 � A 0 1 ! " # / � � � � � � � � � � � � � + $ - . 6 M timetick timer@4ca2000 qcom,timetick �� PSystemTimer [$� f p M timer@4ca3000 qcom,timetick ��0 PWakeUpTimer [$� f p M vdd_mxa qcom,rpmh-arc-regulator �/vcs/vdd_mxa /vcs/vdd_mx � � � � �mx.lvl � M vdd_mxc qcom,rpmh-arc-regulator �/vcs/vdd_mxc � � � � �mxc.lvl � M vdd_cx qcom,rpmh-arc-regulator �/vcs/vdd_cx � � � � �cx.lvl � M vdd_mm qcom,rpmh-arc-regulator �/vcs/vdd_mm � � � � �mmcx.lvl � M pinctrl@f100000 qcom,nord-pinctrl qcom,pinctrl � � � $ s * : ���� - ` c d e f g h F } P Vsummary directconn0 directconn1 directconn2 directconn3 directconn4 directconn5 f yGPIOINTADSP0 M hw_mutex qcom,hw_mutex proc-info _ hw_families � family-01 � � �Y� Y� Y� Y� subsys_instance qcom,subsys_instance � �primary cxstmtrace@16000000 qcom,stmtrace � � � lpistmtrace@5400000 qcom,stmtrace �@ � @ � @ cxstmcfg@10002000 qcom,stmcfg � � � � lpistmcfg@119B2000 qcom,stmcfg �� � � � qdss $ �� � � L� � 0 L0 � �� sw M core cpt_boot_test ` test1 % . >�� J V g�� * sMy Secret Message, Please keep it secret! test2 test_types � .���U � >�� ���U#4 � J� V���������4Vx�eC! � g�� ( ��������穣����4Vx����ܺ�vT2 � test_pic_3 qcom,pic test_uart1 qcom,uart � �base rx tx test_uart2 qcom,uart PD_Access_control OEM_Flavor_Validation debugtools version_tbl qcom,image_version_tbl_idx + eic qcom,eic 5 F U Z err_qdi qcom,err_qdi e �P z � pd_mon audio_process qcom,pd_mon_user_process_config �/ramfs/audio_lpai.mbn 3 �/rfs/root/vendor/firmware_mnt/image/audio_lpai.mbn �audio_process � � � �audio_pd charger_process qcom,pd_mon_user_process_config � � �charger_process � � � �charger_pd qsh_process qcom,pd_mon_user_process_config �/ramfs/qsh.mbn , �/rfs/root/vendor/firmware_mnt/image/qsh.mbn �qsh_process � � � �sensor_pd ois_process qcom,pd_mon_user_process_config �/ramfs/ois_lpai.mbn , �/rfs/root/vendor/firmware_mnt/image/ois.mbn �ois_process � � � �ois_pd pd_mon_restart qcom,pd_mon_restart rcinit qcom,rcinit_cfg rcinit_config_spinor 0 M �d a u0 } � � � � � � � � � � % � A rcinit_config 0 M !4 a � } � � � � � � � � � � % � A servreg qcom,servreg \msm/adsp/root_pd qmsm �adsp �root_pd � J sys_m qcom,sys_m � � � tms_dog qcom,tms_dog ��@ ��@ ��@ �@ �@ #�@ 1�@ < �� T �� m �� � � � � � tms_diag qcom,tms_diag 0 debugtrace qcom,debugtrace qdsp_pm config qcom,config_data , E lpassRegRange Q�p ZP � � l2ConfigRegRange Q Z � cores-array core0 c e j t � � ? � core1 c f j t � � � core2 c i j t � � � core3 c l j t � � � core4 c r j t � � � core5 c | j t r s � � � core6 c � j t � � � core7 c o j t � � � memories-array memory0 � j clocks-array clock0 � � � �/clk/cpu � � j clock1 � � � �hpass_cc_noc_ls_clk � � j clock2 � _ � � ! �hpass_audio_cc_avsync_atime1_clk � � j clock3 � r � � ! �hpass_lpmla_cc_hpass_0_lpmla_clk � � j clock4 � s � � ! �hpass_lpmla_cc_hpass_1_lpmla_clk � � j clock5 � x � � �hpass_cc_enpu_sch_core_clk � � j clock6 � ` � � ! �hpass_audio_cc_avsync_atime2_clk � � j busport-array busPort0 { � , busPort1 { � @ , busPort2 { � @ � , busPort3 { � @ c , busPort4 { � @ d , busPort5 { % � � 7 , % busPort6 { ? � 7 , ? busPort7 { � 7 , busPort8 { > � � 7 � , > extroute-array extBusRoute0 C N % extBusRoute1 C N > extBusRoute2 C N > extBusRoute3 C N % extBusRoute4 C N % mipsroute-array mipsBwRoute0 C N % pwrDomain-array pwrDomain0 j X/core/cpu/latency f � t � � pwrDomain1 j X f � t � � pwrDomain2 j XHMX f � t � � features-array feature0 � � � � � feature1 � � � feature2 � � � feature3 � � �� � ��� feature4 � � � feature5 � � � feature6 � � � feature7 � � � feature8 � � � � ��� feature9 � � � ��� feature10 � � 5�� � ��� feature11 � � /�� � ��� feature12 � � � feature13 � � � � � feature14 � � $=X � ��� feature15 � � �� � '� feature16 � � � feature17 � � � feature18 � � � feature19 � � � feature20 � � � feature21 � � � feature22 � � � feature23 � � � feature24 � � � feature25 � � � feature26 � � � feature27 � � � feature28 � � � feature29 � � � ��� feature30 � � � feature31 � � � feature32 � � � feature33 � � � feature34 � � � feature35 � � � feature36 � � � feature37 � � � config_arch qcom,config_arch compensatedDdrBwTable 0 � �� rp� � 0 � �� ��� � 0 � ܓ� ��� X 0 � �t� �2� � 0 � �U� �2� � 0 � &�6� �� � 0 � ,�� s�� � 0 � 2��� �� � 0 � 8�ـ �� � 0 � >��� �� � 0 �������� �� � adspsnocVoteTable 8 � �� ��� � � ' 8 � �� ��� � � ' 8 � ܓ� ��� X X ' 8 � �t� �2� � � ' 8 � �U� e�� � � ' 8 � &�6� �O� � � ' 8 � ,�� �� � � ' 8 � 2��� �� � � ' 8 � 8�ـ �U� � � ' 8 � >��� *�� � � ' 8 �������� ��� � � ' compensatedLecDdrBwTable 0 � �� ��� X 0 � �� �2� � 0 � � �� � 0 � ׄ s�� � 0 � �e �� � 0 �������� �� � adspLecsnocVoteTable 8 � �� ��� X 8 � �� �2� � 8 � � �O� � 8 � ׄ �� � 8 � �e �U� � 8 �������� ��� � compensatedMlDdrBwTable 0 � �� rp� X 0 � kI� ��� � 0 � Н� �2� � 0 � 8� �� � 0 � G�W s�� � 0 � �n! �� � 0 �������� �� � adspMlsnocVoteTable 8 � �� ��� X 8 � kI� ��� � 8 � Н� �2� � 8 � 8� �O� � 8 � G�W �� � 8 � �n! �U� � 8 �������� ��� � adspToLpiNocFreqTable � �0 $� �$� 5 �3� � �=�P O� �M�� j �bkP $� mlToLpiNocFreqTable �$� $� �O� 5 �RH � � O� �&�� j �0� $� diag qcom,adsp_core_diagcfg diagcfg_cmd , * F = d U } Z � � � � � 2 R k � � � �" � # : S g � �! diagcfg_param � @ � � � , @ X s � � � � � � � � � ' 2 ; P h � @ � � � � � � � � - < H h � � � � � � �K #� 5 � U o �d � � � � $ < V v � � � � � � @ , < K gZ � �QURTOS_ISLAND_POOL �QURTOS_ISLAND_POOL diagcfg_early_log � � _ � � � � � diagcfg_f3_trace ! 7 � Q __symbols__ g/soc k/soc/clock-controller@af00000 u/soc/clock-controller@8d00000 /soc/clock-controller@100000 �/soc/clock-controller@5000000 �/soc/clock-controller@5500000 �/soc/clock-controller@4d80000 �/soc/clock-controller@4c40000 �/soc/clock-controller@8900000 �/soc/clock-controller@8b00000 �/soc/clock-controller@8a00000 �/soc/clock-controller@1f40000 �/soc/cesta@5333000 �/soc/ipcc/ipcc@9002000 �/soc/ipcc/ipcc@90c0000 �/soc/ipcc/ipcc@9180000 /soc/ipcc/ipcc@9240000 /soc/ipcc/ipcc@9300000 #/soc/timetick/timer@4ca2000 //soc/timetick/timer@4ca3000 ;/soc/vdd_mxa C/soc/vdd_mxc K/soc/vdd_cx R/soc/vdd_mm Y/soc/pinctrl@f100000 ^/sw __fixups__ � a/soc/ipcc/ipcc@9002000:interrupt-parent:0 /soc/ipcc/ipcc@90c0000:interrupt-parent:0 /soc/ipcc/ipcc@9180000:interrupt-parent:0 /soc/ipcc/ipcc@9240000:interrupt-parent:0 /soc/ipcc/ipcc@9300000:interrupt-parent:0 /soc/pinctrl@f100000:interrupt-parent:0 model compatible #address-cells #size-cells proc-name chip-info instance-ids phandle smem-this-host smem-version-offset core-top-csr-str tcsr-base mutex-offsets-data wonce-offsets supported-hosts remote-host fifo-size mtu-size irq-out qos-max-rate channel-name mailbox-area-size-bytes master-mailbox-size-bytes max-tx-pending-items is-master mailbox-desc-start host-name id transport remote-ss ch-name options priority stack-size intents host-id fflags max-entries dest proc irq reg reg-names #clock-cells client protocol-name protocol-idx interrupt-parent interrupts #signals client-mapping timer-name timer-freq timer-num timer-interrupt regulator-name regulator-min-microvolt regulator-max-microvolt regulator-init-microvolt qcom,resource-name qcom,all-pd-regulator qcom,lpr-enable qcom,drv-id ngpios width gpio-controller #gpio-cells interrupt-types interrupt-names summary-targetproc global-ctxt-name max_families_supported max_mutex mutex_family mutexs value base_port num_ports atid sync_period dbg_regs pwrdbg_ctrl_reg test_config test_bool1 test_bool2 test_ver test_uint8_list test_uint16 test_uint32 test_uint32_list test_uint64 test_string test_uint8 test_uint8_list_empty test_uint16_list test_uint16_list_empty test_uint32_list_empty test_uint64_list test_uint64_list_empty reg_alt PD_indicator test_oem_entry image_idx eic_crash_enable eic_crash_type eic_crash_delay pd_timeout_exit_msec threshold_timeout_sec num_pdrs_log pd_binary_local_path pd_binary_remote_path pd_name pd_mon_install_attr pd_mon_image_sw_id subdomain_name pd_mon_restart_enable pd_mon_dump_disable rcinit_term_err_fatal_enable rcinit_term_timeout rcinit_term_timeout_group_0 rcinit_term_timeout_group_1 rcinit_term_timeout_group_2 rcinit_term_timeout_group_3 rcinit_term_timeout_group_4 rcinit_term_timeout_group_5 rcinit_term_timeout_group_6 rcinit_term_timeout_group_7 rcinit_term_latency_enable servreg_local_domain servreg_soc_name servreg_domain_name servreg_subdomain_name servreg_qmi_instance_id ssctl_srv sys_m_smem_ssr_res wdog_nmi_time wdog_bite_time wdog_bark_time wdog_status wdog_ctl wdog_bite_nmi wdog_reset wdog_nmi_time_data_bmsk wdog_bite_time_data_bmsk wdog_bark_time_data_bmsk wdog_ctl_wdog_to_nmi_en_bmsk wdog_ctl_wdog_to_nmi_en_shft wdog_ctl_enable_bmsk wdog_ctl_enable_shft wdog_reset_wdog_reset_shft image_id qdss_service_id THREAD_NUMBER OVERHANG_VOTE_TIMEOUT_MS DEBUG_LEVEL baseAddr physAddr coreId pwrDomain coreClockInstances masterBusPortInstances slaveBusPortInstances numInstances memId clkId clkType clkCntlType clkName clkSrcId memoryId portConnection busClk regProgClocks icbarbMaster accessPort icbarbSlave masterPort slavePort pwrDomainName pwrDomainType intrReinitTrigger intrReinitDone securityClocks state min max index0 index1 index2 index3 index4 index5 index6 index7 index8 index9 index10 diag_cmd_request_f diag_start_stress_test_f diag_stress_test_loopback diag_legacy_health_count_base diag_get_max_req_pkt_len diag_delay_health_count_base diag_dcm_cmd_reg_test_base diag_ulogdiag_processor_id diag_subsys_id_base diag_flow_control_count_base diag_dsm_chained_count_base diag_get_cmd_reg_tbl diag_subsys_mask_retrieval_base diag_f3_trace_set_config diag_tx_mode_config diag_stress_test_delayed_rsp diag_drop_threshold_config diag_query_enable diag_get_time_api diag_get_drop_per diag_uimage_health_stats diag_start_stress_test_adv_f diag_health_stats_base diag_get_set_drain_param diag_set_drain_prop diag_health_report_config diag_get_set_client_settings diag_lock_buffer_api diag_instance_id_base diag_err_ulog_size diag_debug_ulog_size diag_cmd_ulog_size diag_data_ulog_size diag_qdss_ulog_size diag_ctrl_ulog_size diag_listener_ulog_size diag_sendbuf_dbg_ulog_size diag_mpd_drain_timer_len diag_mpd_buf_commit_thresh_per diag_mpd_buf_drain_thresh_per diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_drain_timer_len diag_event_send_max diag_event_heap_size diag_ctrl_send_buf_size diag_ctrl_read_buf_size diag_cmd_read_buf_size diag_event_sec_heap_size diag_dci_read_buf_size diag_rsp_heap_size diag_heap_size diag_f3_trace_buf_size diag_buf_size diag_rsp_alloc_retry_timer_len diag_mask_notify_timer_len diag_tx_sleep_threshold_default diag_tx_sleep_time_default diag_core_pd_drain_threshold diag_sio_timeout_timer_len diag_cmd_read_tout_timer_len diag_max_active_listeners diag_many_drain_per_mark diag_few_drain_per_mark diag_hdlc_pad_len diag_stress_task_sleep_complete diag_buf_commit_threshold diag_buffer_default_lock_state diag_drop_flow_cnt_incr diag_drop_per_step_max diag_drop_per_threshold_max diag_deferrable_timer diag_deferrable_timer_ex diag_send_data_buf_size_max diag_min_send_data_size diag_msg_fmt_str_arg_size diag_event_rpt_pkt_len_size_nrt diag_event_rpt_pkt_size_nrt diag_event_send_max_nrt diag_event_timer_len_nrt diag_tx_sleep_threshold_nrt diag_tx_sleep_time_nrt diag_drain_timer_len_nrt diagbuf_commit_threshold_nrt diag_mpd_commit_thresh_nrt_per diag_uimage_drain_timer_len diag_uimage_buf_high_per_wm diag_uimage_f3_trace_buf_size diag_uimage_pool diag_uimage_test_pool diag_early_log_control diag_early_log_mask diag_early_event_mask diag_early_message_mask diag_f3_trace_control diag_f3_trace_detail_mask diag_f3_trace_version soc disp_cc_0 disp_cc_1 gcc hpass_audio_cc hpass_cc hpass_lpmla_cc hpass_q6_cc_0 ne_gcc nw_gcc se_gcc tcsr_cc hpass_cesta ipcc_mproc ipcc_compute_l0 ipcc_compute_l1 ipcc_periph ipcc_fence SystemTimer WakeUpTimer vdd_mxa vdd_mxc vdd_cx vdd_mm tlmm sw intc � �� 8 ` ( � ( qcom,nord qcom,nord board-id % ,audio_process-nord-1.0-adsp-i0-audio 6 � @ soc M cxstmtrace@16000000 qcom,stmtrace U Y � c @ lpistmtrace@5400000 qcom,stmtrace U@ Y c @ subsys_instance qcom,subsys_instance m sprimary sw M core mproc qmi qcsi qcom,qmi_qcsi_user_pd_config qmi_qcsi_ping_server_config | � ! power qdsp_pm pd qcom,pd-audio-process � debugtools tms_diag qcom,tms_diag � � eic qcom,eic � � � Z version_tbl qcom,image_version_tbl_idx � debugtrace qcom,debugtrace � diag qcom,audio_user_diagcfg diagcfg_cmd � g i = ; V j � � � � � diagcfg_param � � � $ � 9 U � m 2 � � � � � � � � 6 P i �AUDIO_ISLAND_TCM_PHYSPOOL �QSH_ISLAND_POOL __symbols__ �/soc �/sw model compatible #address-cells #size-cells proc-name chip-info instance-ids phandle reg base_port num_ports value priority service_id instance_id QDI_QDSP_PM_USER_ID image_id eic_crash_enable eic_crash_type eic_crash_delay image_idx qdss_service_id diag_test_cmd_f diag_v2_test_cmd_f diag_legacy_health_count_base diag_ulogdiag_processor_id diag_subsys_id_base diag_lsm_cmd_reg_test_base diag_get_set_drain_param diag_f3_trace_set_config diag_health_stats_base diag_err_ulog_size diag_debug_ulog_size diag_qdss_ulog_size diag_logtracker_ulog_size diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_event_send_max diag_multipd_buf_size diag_multipd_event_heap_size diag_send_buf_size_data_userpd diag_lsm_stack_size diag_stress_task_sleep_complete diag_deferrable_timer diag_deferrable_timer_ex diag_msg_fmt_str_arg_size diag_uimage_mpd_buf_size diag_uimage_f3_trace_buf_size diag_uimage_pool diag_uimage_test_pool soc sw � �� �� 8 p$ ( f o� qcom,seca qcom,seca board-id ' ,default_process-seca-1.0-adsp-i0-audio 6 � @ soc M smem qcom,smem U d xCORE_TOP_CSR �� � 0 � @ @ glink qcom,glink ` � proc-info _ xport-smem-config edge-01 � � @ � � � N edge-02 � � @ � � � N edge-03 � � @ � � � N edge-04 � � @ � � ! � N edge-05 � � @ � � " � N xport-qmp-config edge-01 �aop_adsp � 7 � L V @ ipc_router qcom,ipc_router proc-info iadsp0 s devcfg-glink-xals edge-01 vSMEM �apss �IPCRTR � �� � � � � � edge-02 vSMEM �apss_1_0_0 �IPCRTR � �� � � � � � edge-03 vSMEM �apss_2_0_0 �IPCRTR � �� � � � � � smp2p qcom,smp2p proc-info � � � smp2p-interrupts intr-01 � � � intr-02 � � � hw_mutex qcom,hw_mutex proc-info _ hw_families � family-01 � Y� Y� Y� Y� subsys_instance qcom,subsys_instance �primary cxstmtrace@16000000 qcom,stmtrace ( lpistmtrace@5400000 qcom,stmtrace @ @ ( @ cxstmcfg@10002000 qcom,stmcfg 2 7 � lpistmcfg@119B2000 qcom,stmcfg � 2 7 � qdss $ C� � � L� � 0 L0 � L� clock-controller@af00000 7 qcom,disp_cc_0-seca qcom,cc-seca qcom,clock-controller 8 � � � �0 �` �p � � ? \MDSS_0_DISP_CC_PLL0_DISP_CC_PLL0_CM_PLL_LUCID_OLE MDSS_0_DISP_CC_PLL1_DISP_CC_PLL1_CM_PLL_LUCID_OLE MDSS_0_DISP_CC_PLL2_DISP_CC_PLL2_CM_PLL_ZONDA_OLE MDSS_0_DISP_CC_PLL3_DISP_CC_PLL3_CM_PLL_ZONDA_OLE MDSS_0_DISP_CC_DISP_CC_AHB2PHY_SWMAN MDSS_0_DISP_CC_DISP_CC_AHB2PHY_BROADCAST_SWMAN MDSS_0_DISP_CC_DISP_CC_DISP_CC_REG f M clock-controller@8d00000 7 qcom,disp_cc_1-seca qcom,cc-seca qcom,clock-controller 8 � � � �0 �` �p Ѐ � ? \MDSS_1_DISP_CC_PLL0_DISP_CC_PLL0_CM_PLL_LUCID_OLE MDSS_1_DISP_CC_PLL1_DISP_CC_PLL1_CM_PLL_LUCID_OLE MDSS_1_DISP_CC_PLL2_DISP_CC_PLL2_CM_PLL_ZONDA_OLE MDSS_1_DISP_CC_PLL3_DISP_CC_PLL3_CM_PLL_ZONDA_OLE MDSS_1_DISP_CC_DISP_CC_AHB2PHY_SWMAN MDSS_1_DISP_CC_DISP_CC_AHB2PHY_BROADCAST_SWMAN MDSS_1_DISP_CC_DISP_CC_DISP_CC_REG f M clock-controller@100000 1 qcom,gcc-seca qcom,cc-seca qcom,clock-controller h 0 @ P ` p � � � / B ? \GCC_GPLL0_CM_PLL_LUCID_OLE GCC_GPLL1_CM_PLL_LUCID_OLE GCC_GPLL2_CM_PLL_LUCID_OLE GCC_GPLL3_CM_PLL_LUCID_OLE GCC_GPLL4_CM_PLL_LUCID_OLE GCC_GPLL5_CM_PLL_LUCID_OLE GCC_GPLL6_CM_PLL_LUCID_OLE GCC_GPLL7_CM_PLL_LUCID_OLE GCC_JBIST_CM_PLL_JBIST4_OLE GCC_AHB2PHY_SWMAN GCC_AHB2PHY_BROADCAST_SWMAN GCC_CLK_CTL_REG GCC_RPU_XPU4 f M clock-controller@5000000 < qcom,hpass_audio_cc-seca qcom,cc-seca qcom,clock-controller 0 ` p � p � \HPASS_AUDIO_CC_PLL1_CM_PLL_ZONDA_OLE HPASS_AUDIO_CC_PLL2_CM_PLL_ZONDA_OLE HPASS_AUDIO_CC_CM_PLL_JBIST4_OLE HPASS_AUDIO_CC_AHB2PHY_SWMAN HPASS_AUDIO_CC_AHB2PHY_BROADCAST_SWMAN HPASS_AUDIO_CC_HPASS_AUDIO_CC_REG f M clock-controller@5500000 6 qcom,hpass_cc-seca qcom,cc-seca qcom,clock-controller ( P P` Pp P� X � � \HPASS_CC_DIG_PLL_CM_PLL_LUCID_OLE HPASS_CC_AHB2PHY_SWMAN HPASS_CC_AHB2PHY_BROADCAST_SWMAN HPASS_CC_HPASS_CC_REG HPASS_HPASS_TCSR_REGS f M clock-controller@4d80000 < qcom,hpass_lpmla_cc-seca qcom,cc-seca qcom,clock-controller � �` �p @ � \HPASS_LPMLA_CC_DIG_PLL_CM_PLL_LUCID_OLE HPASS_LPMLA_CC_AHB2PHY_SWMAN HPASS_LPMLA_CC_AHB2PHY_BROADCAST_SWMAN HPASS_LPMLA_CC_HPASS_LPMLA_CC_REG f M clock-controller@4c40000 ; qcom,hpass_q6_cc_0-seca qcom,cc-seca qcom,clock-controller � Ā � K \HPASS_0_QDSP6SS_PLL_PLL_CM_PLL_LUCID_OLE HPASS_0_QDSP6SS_Q6V81DGB_1_CC_REG f M clock-controller@8900000 4 qcom,ne_gcc-seca qcom,cc-seca qcom,clock-controller p � � � �0 �@ �P �` �p �� �� �� �� � � B � \NE_GCC_GPLL0_CM_PLL_LUCID_OLE NE_GCC_GPLL1_CM_PLL_LUCID_OLE NE_GCC_GPLL2_CM_PLL_LUCID_OLE NE_GCC_GPLL3_CM_PLL_LUCID_OLE NE_GCC_GPLL4_CM_PLL_LUCID_OLE NE_GCC_GPLL5_CM_PLL_ZONDA_OLE NE_GCC_GPLL6_CM_PLL_ZONDA_OLE NE_GCC_GPLL7_CM_PLL_ZONDA_OLE NE_GCC_GPLL8_CM_PLL_ZONDA_OLE NE_GCC_JBIST_CM_PLL_JBIST4_OLE NE_GCC_AHB2PHY_SWMAN NE_GCC_AHB2PHY_BROADCAST_SWMAN NE_GCC_NE_CLK_CTL_REG NE_GCC_RPU_XPU4 f M clock-controller@8b00000 4 qcom,nw_gcc-seca qcom,cc-seca qcom,clock-controller P � � � �0 �@ �P �� �� � � B \NW_GCC_GPLL0_CM_PLL_LUCID_OLE NW_GCC_GPLL1_CM_PLL_LUCID_OLE NW_GCC_GPLL2_CM_PLL_LUCID_OLE NW_GCC_GPLL3_CM_PLL_LUCID_OLE NW_GCC_GPLL4_CM_PLL_LUCID_OLE NW_GCC_GPLL5_CM_PLL_LUCID_OLE NW_GCC_AHB2PHY_SWMAN NW_GCC_AHB2PHY_BROADCAST_SWMAN NW_GCC_NW_CLK_CTL_REG NW_GCC_RPU_XPU4 f M clock-controller@8a00000 4 qcom,se_gcc-seca qcom,cc-seca qcom,clock-controller h � � � �0 �@ �P �` �p �� �� �� � � B i \SE_GCC_GPLL0_CM_PLL_LUCID_OLE SE_GCC_GPLL1_CM_PLL_LUCID_OLE SE_GCC_GPLL2_CM_PLL_LUCID_OLE SE_GCC_GPLL3_CM_PLL_LUCID_OLE SE_GCC_GPLL4_CM_PLL_LUCID_OLE SE_GCC_GPLL5_CM_PLL_LUCID_OLE SE_GCC_GPLL6_CM_PLL_LUCID_OLE SE_GCC_GPLL7_CM_PLL_LUCID_OLE SE_GCC_JBIST_CM_PLL_JBIST4_OLE SE_GCC_AHB2PHY_SWMAN SE_GCC_AHB2PHY_BROADCAST_SWMAN SE_GCC_SE_CLK_CTL_REG SE_GCC_RPU_XPU4 f M clock-controller@1f40000 5 qcom,tcsr_cc-seca qcom,cc-seca qcom,clock-controller � � \TCSR_TCSR_REGS TLMM_REG f M cesta@5333000 # qcom,hpass_cesta-seca qcom,cc-seca ( 30 34 38 3X 3^ @ \HPASS_CRMB HPASS_CRMB_PT HPASS_CRMC HPASS_CRMV HPASS_CRM_COMMON M ipcc qcom,ipcc ipcc@9002000 qcom,ipcc-protocol s zMPROC � ����� � . � d � 0 1 ! " # $ - . 4 5 2 3 M ipcc@90c0000 qcom,ipcc-protocol s zCOMPUTE_L0 � ����� � + � t � 0 1 ! " # / + $ - . 2 3 6 M ipcc@9180000 qcom,ipcc-protocol s zCOMPUTE_L1 � ����� � , � t � 0 1 ! " # / + $ - . 2 3 6 M ipcc@9240000 qcom,ipcc-protocol s zPERIPH � ����� � / � < � 0 1 ! " # $ - M ipcc@9300000 qcom,ipcc-protocol s zFENCE � ����� � - � � � 0 1 ! " # / � � � � � � � � � � � � � + $ - . 6 M pinctrl@f100000 qcom,seca-pinctrl qcom,pinctrl � � � � s � � ����� � ` c d e f g h � } P summary directconn0 directconn1 directconn2 directconn3 directconn4 directconn5 %GPIOINTADSP0 M timetick timer@4ca2000 qcom,timetick � 6SystemTimer A$� L V M timer@4ca3000 qcom,timetick �0 6WakeUpTimer A$� L V M vdd_mxa qcom,rpmh-arc-regulator f/vcs/vdd_mxa /vcs/vdd_mx u � � � �mx.lvl � � � M vdd_mxc qcom,rpmh-arc-regulator f/vcs/vdd_mxc u � � � �mxc.lvl � � � M vdd_cx qcom,rpmh-arc-regulator f/vcs/vdd_cx u � � � �cx.lvl � � � M vdd_mm qcom,rpmh-arc-regulator f/vcs/vdd_mm u � � � �mmcx.lvl � � � M sw M core cpt_boot_test ` test1 % . >�� J V g�� * sMy Secret Message, Please keep it secret! test2 test_types � .���U � >�� ���U#4 � J� V���������4Vx�eC! � g�� ( ��������穣����4Vx����ܺ�vT2 � test_pic_3 qcom,pic test_uart1 qcom,uart � \base rx tx test_uart2 qcom,uart PD_Access_control OEM_Flavor_Validation debugtools version_tbl qcom,image_version_tbl_idx + eic qcom,eic 5 F U Z err_qdi qcom,err_qdi e �P z � pd_mon audio_process qcom,pd_mon_user_process_config �/ramfs/audio_lpai.mbn 3 �/rfs/root/vendor/firmware_mnt/image/audio_lpai.mbn �audio_process � � � �audio_pd charger_process qcom,pd_mon_user_process_config � � �charger_process � � � �charger_pd qsh_process qcom,pd_mon_user_process_config �/ramfs/qsh.mbn , �/rfs/root/vendor/firmware_mnt/image/qsh.mbn �qsh_process � � � �sensor_pd ois_process qcom,pd_mon_user_process_config �/ramfs/ois_lpai.mbn , �/rfs/root/vendor/firmware_mnt/image/ois.mbn �ois_process � � � �ois_pd pd_mon_restart qcom,pd_mon_restart rcinit qcom,rcinit_cfg rcinit_config_spinor 0 M �d a u0 } � � � � � � � � � � % � A rcinit_config 0 M !4 a � } � � � � � � � � � � % � A servreg qcom,servreg \msm/adsp/root_pd qmsm �adsp �root_pd � J sys_m qcom,sys_m � � � tms_dog qcom,tms_dog ��@ ��@ ��@ �@ �@ #�@ 1�@ < �� T �� m �� � � � � � tms_diag qcom,tms_diag 0 debugtrace qcom,debugtrace qdsp_pm config qcom,config_data , E lpassRegRange Q�p ZP � � l2ConfigRegRange Q Z � cores-array core0 c e j t � � ? � core1 c f j t � � � core2 c i j t � � � core3 c l j t � � � core4 c r j t � � � core5 c | j t r s � � � core6 c � j t � � � core7 c o j t � � � memories-array memory0 � j clocks-array clock0 � � � �/clk/cpu � � j clock1 � � � �hpass_cc_noc_ls_clk � � j clock2 � _ � � ! �hpass_audio_cc_avsync_atime1_clk � � j clock3 � r � � ! �hpass_lpmla_cc_hpass_0_lpmla_clk � � j clock4 � s � � ! �hpass_lpmla_cc_hpass_1_lpmla_clk � � j clock5 � x � � �hpass_cc_enpu_sch_core_clk � � j clock6 � ` � � ! �hpass_audio_cc_avsync_atime2_clk � � j busport-array busPort0 { � , busPort1 { � @ , busPort2 { � @ � , busPort3 { � @ c , busPort4 { � @ d , busPort5 { % � � 7 , % busPort6 { ? � 7 , ? busPort7 { � 7 , busPort8 { > � � 7 � , > extroute-array extBusRoute0 C N % extBusRoute1 C N > extBusRoute2 C N > extBusRoute3 C N % extBusRoute4 C N % mipsroute-array mipsBwRoute0 C N % pwrDomain-array pwrDomain0 j X/core/cpu/latency f � t � � pwrDomain1 j X f � t � � pwrDomain2 j XHMX f � t � � features-array feature0 � � � � � feature1 � � � feature2 � � � feature3 � � �� � ��� feature4 � � � feature5 � � � feature6 � � � feature7 � � � feature8 � � � � ��� feature9 � � � ��� feature10 � � 5�� � ��� feature11 � � /�� � ��� feature12 � � � feature13 � � � � � feature14 � � $=X � ��� feature15 � � �� � '� feature16 � � � feature17 � � � feature18 � � � feature19 � � � feature20 � � � feature21 � � � feature22 � � � feature23 � � � feature24 � � � feature25 � � � feature26 � � � feature27 � � � feature28 � � � feature29 � � � ��� feature30 � � � feature31 � � � feature32 � � � feature33 � � � feature34 � � � feature35 � � � feature36 � � � feature37 � � � config_arch qcom,config_arch compensatedDdrBwTable 0 � �� rp� � 0 � �� ��� � 0 � ܓ� ��� X 0 � �t� �2� � 0 � �U� �2� � 0 � &�6� �� � 0 � ,�� s�� � 0 � 2��� �� � 0 � 8�ـ �� � 0 � >��� �� � 0 �������� �� � adspsnocVoteTable 8 � �� ��� � � ' 8 � �� ��� � � ' 8 � ܓ� ��� X X ' 8 � �t� �2� � � ' 8 � �U� e�� � � ' 8 � &�6� �O� � � ' 8 � ,�� �� � � ' 8 � 2��� �� � � ' 8 � 8�ـ �U� � � ' 8 � >��� *�� � � ' 8 �������� ��� � � ' compensatedLecDdrBwTable 0 � �� ��� X 0 � �� �2� � 0 � � �� � 0 � ׄ s�� � 0 � �e �� � 0 �������� �� � adspLecsnocVoteTable 8 � �� ��� X 8 � �� �2� � 8 � � �O� � 8 � ׄ �� � 8 � �e �U� � 8 �������� ��� � compensatedMlDdrBwTable 0 � �� rp� X 0 � kI� ��� � 0 � Н� �2� � 0 � 8� �� � 0 � G�W s�� � 0 � �n! �� � 0 �������� �� � adspMlsnocVoteTable 8 � �� ��� X 8 � kI� ��� � 8 � Н� �2� � 8 � 8� �O� � 8 � G�W �� � 8 � �n! �U� � 8 �������� ��� � adspToLpiNocFreqTable � �0 $� �$� 5 �3� � �=�P O� �M�� j �bkP $� mlToLpiNocFreqTable �$� $� �O� 5 �RH � � O� �&�� j �0� $� diag qcom,adsp_core_diagcfg diagcfg_cmd , * F = d U } Z � � � � � 2 R k � � � �" � # : S g � �! diagcfg_param � @ � � � , @ X s � � � � � � � � � ' 2 ; P h � @ � � � � � � � � - < H h � � � � � � �K #� 5 � U o �d � � � � $ < V v � � � � � � @ , < K gZ � �QURTOS_ISLAND_POOL �QURTOS_ISLAND_POOL diagcfg_early_log � � _ � � � � � diagcfg_f3_trace ! 7 � Q __symbols__ g/soc k/soc/clock-controller@af00000 u/soc/clock-controller@8d00000 /soc/clock-controller@100000 �/soc/clock-controller@5000000 �/soc/clock-controller@5500000 �/soc/clock-controller@4d80000 �/soc/clock-controller@4c40000 �/soc/clock-controller@8900000 �/soc/clock-controller@8b00000 �/soc/clock-controller@8a00000 �/soc/clock-controller@1f40000 �/soc/cesta@5333000 �/soc/ipcc/ipcc@9002000 �/soc/ipcc/ipcc@90c0000 �/soc/ipcc/ipcc@9180000 /soc/ipcc/ipcc@9240000 /soc/ipcc/ipcc@9300000 #/soc/pinctrl@f100000 (/soc/timetick/timer@4ca2000 4/soc/timetick/timer@4ca3000 @/soc/vdd_mxa H/soc/vdd_mxc P/soc/vdd_cx W/soc/vdd_mm ^/sw __fixups__ � a/soc/ipcc/ipcc@9002000:interrupt-parent:0 /soc/ipcc/ipcc@90c0000:interrupt-parent:0 /soc/ipcc/ipcc@9180000:interrupt-parent:0 /soc/ipcc/ipcc@9240000:interrupt-parent:0 /soc/ipcc/ipcc@9300000:interrupt-parent:0 /soc/pinctrl@f100000:interrupt-parent:0 model compatible #address-cells #size-cells proc-name chip-info instance-ids phandle smem-this-host smem-version-offset core-top-csr-str tcsr-base mutex-offsets-data wonce-offsets supported-hosts remote-host fifo-size mtu-size irq-out qos-max-rate channel-name mailbox-area-size-bytes master-mailbox-size-bytes max-tx-pending-items is-master mailbox-desc-start host-name id transport remote-ss ch-name options priority stack-size intents host-id fflags max-entries dest proc irq max_families_supported max_mutex mutex_family mutexs value reg base_port num_ports atid sync_period dbg_regs pwrdbg_ctrl_reg reg-names #clock-cells client protocol-name protocol-idx interrupt-parent interrupts #signals client-mapping ngpios width gpio-controller #gpio-cells interrupt-types interrupt-names summary-targetproc global-ctxt-name timer-name timer-freq timer-num timer-interrupt regulator-name regulator-min-microvolt regulator-max-microvolt regulator-init-microvolt qcom,resource-name qcom,all-pd-regulator qcom,lpr-enable qcom,drv-id test_config test_bool1 test_bool2 test_ver test_uint8_list test_uint16 test_uint32 test_uint32_list test_uint64 test_string test_uint8 test_uint8_list_empty test_uint16_list test_uint16_list_empty test_uint32_list_empty test_uint64_list test_uint64_list_empty reg_alt PD_indicator test_oem_entry image_idx eic_crash_enable eic_crash_type eic_crash_delay pd_timeout_exit_msec threshold_timeout_sec num_pdrs_log pd_binary_local_path pd_binary_remote_path pd_name pd_mon_install_attr pd_mon_image_sw_id subdomain_name pd_mon_restart_enable pd_mon_dump_disable rcinit_term_err_fatal_enable rcinit_term_timeout rcinit_term_timeout_group_0 rcinit_term_timeout_group_1 rcinit_term_timeout_group_2 rcinit_term_timeout_group_3 rcinit_term_timeout_group_4 rcinit_term_timeout_group_5 rcinit_term_timeout_group_6 rcinit_term_timeout_group_7 rcinit_term_latency_enable servreg_local_domain servreg_soc_name servreg_domain_name servreg_subdomain_name servreg_qmi_instance_id ssctl_srv sys_m_smem_ssr_res wdog_nmi_time wdog_bite_time wdog_bark_time wdog_status wdog_ctl wdog_bite_nmi wdog_reset wdog_nmi_time_data_bmsk wdog_bite_time_data_bmsk wdog_bark_time_data_bmsk wdog_ctl_wdog_to_nmi_en_bmsk wdog_ctl_wdog_to_nmi_en_shft wdog_ctl_enable_bmsk wdog_ctl_enable_shft wdog_reset_wdog_reset_shft image_id qdss_service_id THREAD_NUMBER OVERHANG_VOTE_TIMEOUT_MS DEBUG_LEVEL baseAddr physAddr coreId pwrDomain coreClockInstances masterBusPortInstances slaveBusPortInstances numInstances memId clkId clkType clkCntlType clkName clkSrcId memoryId portConnection busClk regProgClocks icbarbMaster accessPort icbarbSlave masterPort slavePort pwrDomainName pwrDomainType intrReinitTrigger intrReinitDone securityClocks state min max index0 index1 index2 index3 index4 index5 index6 index7 index8 index9 index10 diag_cmd_request_f diag_start_stress_test_f diag_stress_test_loopback diag_legacy_health_count_base diag_get_max_req_pkt_len diag_delay_health_count_base diag_dcm_cmd_reg_test_base diag_ulogdiag_processor_id diag_subsys_id_base diag_flow_control_count_base diag_dsm_chained_count_base diag_get_cmd_reg_tbl diag_subsys_mask_retrieval_base diag_f3_trace_set_config diag_tx_mode_config diag_stress_test_delayed_rsp diag_drop_threshold_config diag_query_enable diag_get_time_api diag_get_drop_per diag_uimage_health_stats diag_start_stress_test_adv_f diag_health_stats_base diag_get_set_drain_param diag_set_drain_prop diag_health_report_config diag_get_set_client_settings diag_lock_buffer_api diag_instance_id_base diag_err_ulog_size diag_debug_ulog_size diag_cmd_ulog_size diag_data_ulog_size diag_qdss_ulog_size diag_ctrl_ulog_size diag_listener_ulog_size diag_sendbuf_dbg_ulog_size diag_mpd_drain_timer_len diag_mpd_buf_commit_thresh_per diag_mpd_buf_drain_thresh_per diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_drain_timer_len diag_event_send_max diag_event_heap_size diag_ctrl_send_buf_size diag_ctrl_read_buf_size diag_cmd_read_buf_size diag_event_sec_heap_size diag_dci_read_buf_size diag_rsp_heap_size diag_heap_size diag_f3_trace_buf_size diag_buf_size diag_rsp_alloc_retry_timer_len diag_mask_notify_timer_len diag_tx_sleep_threshold_default diag_tx_sleep_time_default diag_core_pd_drain_threshold diag_sio_timeout_timer_len diag_cmd_read_tout_timer_len diag_max_active_listeners diag_many_drain_per_mark diag_few_drain_per_mark diag_hdlc_pad_len diag_stress_task_sleep_complete diag_buf_commit_threshold diag_buffer_default_lock_state diag_drop_flow_cnt_incr diag_drop_per_step_max diag_drop_per_threshold_max diag_deferrable_timer diag_deferrable_timer_ex diag_send_data_buf_size_max diag_min_send_data_size diag_msg_fmt_str_arg_size diag_event_rpt_pkt_len_size_nrt diag_event_rpt_pkt_size_nrt diag_event_send_max_nrt diag_event_timer_len_nrt diag_tx_sleep_threshold_nrt diag_tx_sleep_time_nrt diag_drain_timer_len_nrt diagbuf_commit_threshold_nrt diag_mpd_commit_thresh_nrt_per diag_uimage_drain_timer_len diag_uimage_buf_high_per_wm diag_uimage_f3_trace_buf_size diag_uimage_pool diag_uimage_test_pool diag_early_log_control diag_early_log_mask diag_early_event_mask diag_early_message_mask diag_f3_trace_control diag_f3_trace_detail_mask diag_f3_trace_version soc disp_cc_0 disp_cc_1 gcc hpass_audio_cc hpass_cc hpass_lpmla_cc hpass_q6_cc_0 ne_gcc nw_gcc se_gcc tcsr_cc hpass_cesta ipcc_mproc ipcc_compute_l0 ipcc_compute_l1 ipcc_periph ipcc_fence tlmm SystemTimer WakeUpTimer vdd_mxa vdd_mxc vdd_cx vdd_mm sw intc � �� 8 ` ( � ( qcom,seca qcom,seca board-id % ,audio_process-seca-1.0-adsp-i0-audio 6 � @ soc M cxstmtrace@16000000 qcom,stmtrace U Y � c @ lpistmtrace@5400000 qcom,stmtrace U@ Y c @ subsys_instance qcom,subsys_instance m sprimary sw M core mproc qmi qcsi qcom,qmi_qcsi_user_pd_config qmi_qcsi_ping_server_config | � ! power qdsp_pm pd qcom,pd-audio-process � debugtools tms_diag qcom,tms_diag � � eic qcom,eic � � � Z version_tbl qcom,image_version_tbl_idx � debugtrace qcom,debugtrace � diag qcom,audio_user_diagcfg diagcfg_cmd � g i = ; V j � � � � � diagcfg_param � � � $ � 9 U � m 2 � � � � � � � � 6 P i �AUDIO_ISLAND_TCM_PHYSPOOL �QSH_ISLAND_POOL __symbols__ �/soc �/sw model compatible #address-cells #size-cells proc-name chip-info instance-ids phandle reg base_port num_ports value priority service_id instance_id QDI_QDSP_PM_USER_ID image_id eic_crash_enable eic_crash_type eic_crash_delay image_idx qdss_service_id diag_test_cmd_f diag_v2_test_cmd_f diag_legacy_health_count_base diag_ulogdiag_processor_id diag_subsys_id_base diag_lsm_cmd_reg_test_base diag_get_set_drain_param diag_f3_trace_set_config diag_health_stats_base diag_err_ulog_size diag_debug_ulog_size diag_qdss_ulog_size diag_logtracker_ulog_size diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_event_send_max diag_multipd_buf_size diag_multipd_event_heap_size diag_send_buf_size_data_userpd diag_lsm_stack_size diag_stress_task_sleep_complete diag_deferrable_timer diag_deferrable_timer_ex diag_msg_fmt_str_arg_size diag_uimage_mpd_buf_size diag_uimage_f3_trace_buf_size diag_uimage_pool diag_uimage_test_pool soc sw � � h S '� � VU �=� � n�Je����n�2c�}4'�I~�3�J%�\�Ѫ�<3��xJ���������~Z4y�� �k}r��N�wʄ,LS��W? p���xJ���������~Z4y�� �k}r��N�wʄ,LS��W? p�� 0e1 ��Wva�jW�J����K�H�=0+�е�7�_� T� �j J���� �E0SL`+ }�kF���,����`�^��Z �I3{f���� 0��0�:�0 *�H�=0��1 0 UUS1,0*U#SECTOOLS SECP384R1 CURVE TEST ROOT010U San Diego10U QUALCOMM10U CDMA Technologies1200U )General Use Test Key 0 (for testing only)0 260820061102Z 460815061102Z0f1 0 UUS10U California10USecTools Test User10U SecTools10U San Diego0v0*�H�=+� "b -ƥ�TX��(v�4i��%�'���9��JH��jK�j�zU�e�9�=e �{���PU�8� o�fJQ��ȅ6ē�L���ݼ��> 69l�f�o0m0 U #0���w���DM2�@tXϙ�L�0 U 0 0 U �0U % 0 +0 U ^I�i7 ����\�vx4��O0 *�H�=g 0d0CJ��p�r銱?�^+E�.ˆx�Cr�� �'�2 !�6 �~�� ��@��0&H" ��$�R56D�G��"K$w`��I{��(� ��[ZP\��L�o���0��0�u�0 *�H�=0��1 0 UUS1+0)U"SECTOOLS SECP384R1 CURVE TEST ROOT10U San Diego10U QUALCOMM10U CDMA Technologies100.U 'General Use Test Key (for testing only)0 160321215215Z 360316215215Z0��1 0 UUS1,0*U#SECTOOLS SECP384R1 CURVE TEST ROOT010U San Diego10U QUALCOMM10U CDMA Technologies1200U )General Use Test Key 0 (for testing only)0v0*�H�=+� "b �T�}� �I%���O�[�H���p� ���]�� f�{�I/C#�9g@�q�Kx�?jE���yAs�Ԝh�'�$,���H pe���y�py�P5��`0^0 U #0�o�q�'�� s� ֟>q�b0 U ��w���DM2�@tXϙ�L�0U 0� 0 U 0 *�H�=i 0f1 � _H��9<�}��� ͣ�����b�:v࣮^6��+<�[ ��61 �ft���Wzcv�ž�$��ֱ(9� � @� n���)f��>�F�߲40��0�N�0 *�H�=0��1 0 UUS1+0)U"SECTOOLS SECP384R1 CURVE TEST ROOT10U San Diego10U QUALCOMM10U CDMA Technologies100.U 'General Use Test Key (for testing only)0 160321215211Z 360316215211Z0��1 0 UUS1+0)U"SECTOOLS SECP384R1 CURVE TEST ROOT10U San Diego10U QUALCOMM10U CDMA Technologies100.U 'General Use Test Key (for testing only)0v0*�H�=+� "b 3��x�~� �ҩ���/פ{���Py�jh`��7_�줎��j^��K1o�$�lTg ]���ء�[�SQ�q6 /�PZ����o�T:ާ�%i�1>}���`�<0:0 U o�q�'�� s� ֟>q�b0 U 0�0 U 0 *�H�=h 0e0u�(�C9�u���T(&�\�L<�t���Bv���ɿ�xJ��܀s6U�1 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